參數(shù)資料
型號(hào)： KM4216C258
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM)
中文描述： 256K × 16位的CMOS視頻RAM（256K × 16位的CMOS視頻內(nèi)存）
文件頁(yè)數(shù)： 18/41頁(yè)
文件大?。?/td> 772K
代理商： KM4216C258
KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
DEVICE OPERATIONS
( Continued)
Transfer Operation
Transfer operation is initiated when DT/OE is low at the falling
edge of RAS. The state of DSF when RAS goes low is used to
select between normal transfer and split transfer cycle. Each of
the transfer cycle is described in the truth table for transfer oper-
ation (Table 1).
Read Transfer (RT)
The Read Transfer operation is set if DT/OE is low, WB/WE is
high and DSF low at the falling edge of RAS. The row address
bits in the read transfer cycle indicate which sixteen 512bit
DRAM row portions are transferred to the sixteen SAM data reg-
ister portions. The column address bits indicate the start address
of the SAM Registers when SAM data read operation is per-
formed. If MSB of column address is low during Read transfer
operation, the QSF state will be set low level and this indicates
the start address of SAM register is present at lower half of SAM
port. (If A
8
is high, QSF will be high and means the start address
is in upper half) Read Transfer may be accomplished in two
ways. If the transfer is to be synchronized with the SC. DT/OE is
taken high after CAS goes low. This is usually called "Real Time
Read Transfer". Note that the rising edge of DT/OE must be
synchronized with the rising edge of SC(
t
TSL
/
t
TSD
) to retain the
continuity of serial read data output. If the transfer does not have
to be synchronized with SC, DT/OE may go high before CAS
goes low and the actual data transfer will be timed internally.
Split Read Transfer (SRT)
In a graphic system, if data has to be transferred from DRAM to
SAM while in the middle of a display line, the only way to do this
seamlessly is performed by a Real Time Read Transfer cycle.
However, this cycle has many critical timing restriction (between
SC, DT/OE, RAS and CAS) because the transfer has to occur at
the first rising edge of DT/OE
The split read transfer(SRT) cycle eliminates the need for this
critical transfer timing, thereby simplifying system design. This is
accomplished by dividing the SAM port into 2 halves of 256 bits
each. A Split Read Transfer loads only the lower or upper half.
While data is being serially read from one half of the SAM Regis-
ter, new RAM data can be transferred to the other half. Since
transfer timing is controlled internally, there is no timing restric-
tion between DT/OE and RAS, CAS, SC.
A normal Read Transfer cycle must be executed before per-
forming a Split Read Transfer to set the state of QSF. A Split
Read Transfer cycle is initiated by keeping DSF and WB/WE
high and DT/OE low at the falling edge of RAS.
Address :
The row address is latched on the falling edge of
RAS. The column address defined by (A
0
~ A
7
) defines the start-
ing address of the SAM port from which data will begin shifting
out. Column address pin A
8
is
a
"
Don
′
t Care."
The QSF pin indicates which SAM half is shifting out serial data
( 0 = Lower, 1 = Upper ). A Split Read Transfer will load data
into the other half. The state of the QSF output changes when
the SAM address counter reaches a split SAM boundary
(e.g. 255th or 511th bit).
Examples of SRT application are shown in Fig. 7 through
Fig.10.
The normal usage of Split Read Transfer cycle is described in
Fig.7. When Read Transfer is executed, data from X1 row
address is fully transferred to the SAM port and serial Read is
started from 0 (Tap address).
If SRT is performed while data is being serially read from lower
half SAM, data from X2 row address is transferred to upper half
SAM. The Tap address of SRT is loaded after the boundary
location of lower half SAM (255th SC) is accessed and the QSF
state is changed into high level at the rising edge of 255th SC.
Note that in this case "256+Y0" Tap address instead of "Y0" is
loaded.
The another example of SRT cycle is described in Fig.8.
When Serial Read is performed after executing RT and SRT in
succession, the data accessed by first SC is the starting
address given by RT Tap address. Serial data access from the
starting address given by SRT cycle is performed after the data
of RT to lower boundary (255th SC) is completed. Fig. 9 and 10
are the example of abnormal SRT cycle.
Table.1 Truth Table for Transfer Operation
RAS Falling Edge
Function
Transfer
Direction
Transfer
Data Bit
CAS
DT/OE
WB/WE
DSF
SE
H
H
L
L
H
H
L
H
*
*
Read Transfer
Split Read Transfer
RAM SAM
RAM SAM
512 x 16
256 x 16
* : Don
′
t care
相關(guān)PDF資料
PDF描述
KM424C64-10 64K X 4 Bit CMOS VIDEO RAM
KM424C64-12 Circular Connector; No. of Contacts:37; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:15-35
KM424C64Z 64K X 4 Bit CMOS VIDEO RAM
KM432C515 512K x 32Bit CMOS Quad CAS DRAM with EDO(512K x 32位CMOS四 CAS 動(dòng)態(tài)RAM(帶EDO模式))
KM432S2030B 512K x 32Bit x 4 Banks Synchronous DRAM(512K x 32位 x 4 組同步動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM4216V256 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256K X 16 BIT CMOS VIDEO RAM
KM4-21L-13PN 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk
KM4-21L-13PN-MK2 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk
KM4-21L-13SN 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk
KM4-21L-13SN-MK2 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*