參數(shù)資料
型號： KM4216C258
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM)
中文描述： 256K × 16位的CMOS視頻RAM（256K × 16位的CMOS視頻內(nèi)存）
文件頁數(shù)： 12/41頁
文件大?。?/td> 772K
代理商： KM4216C258
KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
DEVICE OPERATIONS
( Continued)
2 CAS Byte/Word Read/ Write Operation
The KM4216C258 has 2 CAS control pin, CASL and CASU, and
offers asynchronous Read/Write operation with lower byte (W
0
/
DQ
0
~ W
7
/DQ
7
) and upper byte (W
8
/DQ
8
~ W
15
/DQ
15
). This is
called 2CAS Byte/Word Read/Write operation. This operation
can be performed in any RAM Read in RAM Write, Block Write,
Load Mask Register, and Load Color Register.
New Masked Write Per Bit
The New Masked Write per Bit cycle is achieved by maintaining
CAS high and WB/WE and DSF low at the falling edge of RAS.
The mask data on the W
0
/DQ
0
~ W
15
/DQ
15
pins are latched into
the write mask register at the falling edge of RAS. When the
mask data is low, writing is inhibited into the RAM and the mask
data is high, data is written into the RAM. The mask data is valid
for only one cycle. Mask Data must be provided in every write
cycle that a masking operation is desired.
The Early Write cycle is achieved by WB/WE low before CAS
falling and the Late Write cycle is achieved by WB/WE low after
CAS falling. During the Early or Late Write cycle, input data
through W
0
/DQ
0
~ W
15
/DQ
15
must keep the set-up and hold
time at the falling edge of CAS or WB/WE .
If WB/WE is high at the falling edge of RAS, no masking opera-
tion is performed (see Figure 2,3).
And if CASL is high during WB/WE low, write operation of lower
byte does not perform and if CASU is high, also write operation
of upper byte does not execute.
Load Mask Register (LMR)
The Load Mask Register operation loads the data present on the
Wi/DQi pins into the Mask Data Register at the falling edge of
CAS or WB/WE. The LMR cycle is performed if DSF high,
WB/WE high at the RAS falling edge and DSF low at the CAS
falling edge. If an LMR is done, the KM4216C258 are set to Old
masked write mode.
Old Masked Write Per Bit
This mode is enabled through the Load Mask Register (LMR)
cycle. If an LMR is done, all Masked Write are Old masked Write
Per Bit and the I/O mask data will be provided by the Mask Data
Register (see Figure 4).
The mask data is applied in the same manner as in New Masked
Write Per Bit mode. Mask Data Register
′
s content is changed by
the another LMR, To reset the device back to the New Masked
Write Mode, CBRR(CBR Refresh with option reset) cycle must
be performed. After power-up, the KM4216C258 initializes in the
New Masked Write Mode.
EARLY WRITE
RAS
CASL
WB/WE
W
0
/DQ
0
~W
7
/DQ
7
W
8
/DQ
8
~W
15
/DQ
15
LATE WRITE
Lower Byte Masked Early Write
Upper Byte Masked Early Write
Valid Data-in CASL Falling
Lower Byte Masked Late Write
Upper Byte Masked Late Write
Valid Data-in WB/WE Falling earlier
Mask Data
Mask Data
Valid Data-in
Valid Data-in
t
MS
t
MH
t
DS
t
DH
t
MS
t
MH
t
DS
t
DH
CASU
Figure 2. Byte Write and New Masked Write Cycle Example1. (Early Write & Late Write)
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