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參數資料
| 型號： | KM4216C258 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM) |
| 中文描述： | 256K × 16位的CMOS視頻RAM（256K × 16位的CMOS視頻內存） |
| 文件頁數： | 17/41頁 |
| 文件大小： | 772K |
| 代理商： | KM4216C258 |
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KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
DEVICE OPERATIONS
( Continued)
Data Output
The KM4216C258 has three state output buffer controlled by
DT/OE and CAS/RAS. If DT/OE is high when CAS and RAS
low, the output state is high impedance (High-z). In any cycle,
the output goes low impedance state after
t
CLZ
of the first CAS
falling edge. Invalid data may be present at the output during the
time after
t
CLZ
and the valid data appears at the output. The tim-
ing parameter
t
RAC
,
t
CAC
and
t
AA
specify when the valid data will
be present at the output.
Refresh
The data in the KM4216C258 is stored on a tiny capacitor within
each memory cell. Due to leakage the data may leak off after a
period of time. To maintain data integrity it is necessary to
refresh each of the 512 rows every 8 ms. Any operation cycle
performed in the RAM port refreshes the 8192 bits selected by
the row addresses or an on-chip refresh address counter. Either
a burst refresh or distributed refresh may be used. There are
several ways to accomplish this.
RAS-Only Refresh
This is the most common method for performing refresh. it is
performed by strobing in a row address with RAS while CAS
remains high. This cycle must be repeated for each of the 512
row address, (A
0
~ A
8
).
CAS-Before-RAS Refresh
The KM4216C258 has CAS-before-RAS on chip refresh capabil-
ity that eliminates the need for external refresh address. If CAS
is held low for the specified set up time(
t
CSR
) before RAS goes
low, the on chip refresh circuitry is enabled.
An internal refresh operation occurs automatically. The refresh
address is supplied by the on chip refresh address counter
which is then internally incremented in preparation for the next
CAS-before-RAS refresh cycle.
The KM4216C258 has 3 type CAS-before-RAS refresh opera-
tions CBRR, CBRN, CBRS
CBRR (CBR Refresh with option reset) is set if DSF low at the
RAS falling edge. This mode initiates to change from old
masked write to new masked write cycle, and reset stop regis-
ter to default values.
CBRN (CBR refresh without reset) is set if DSF high when WB/
WE is high at the falling edge of RAS and simply does only
refresh operation.
CBRS (CBR Refresh with stop register set) cycle is set if DSF
high when WB/WE is low and this mode is to set stop register
′
s
value.
Hidden Refresh :
A hidden refresh cycle may be performed while maintaining the
latest valid data at the output by extending the CAS active time
and cycling RAS. The KM4216C258 hidden refresh cycle is
actually a CAS-before-RAS refresh cycle within an extended
read cycle.
The refresh row address is provided by the on-chip refresh
address counter.
Other Refresh Methods :
It is also possible to refresh the KM4216C258 by using read,
write or read-modify-write cycles. Whenever a row is accessed,
all the cells in that row are automatically refreshed. There are
certain applications in which it might be advantageous to per-
form refresh in this manner but in general RAS-only or CAS-
before-RAS refresh is the preferred method.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| KM4216V256 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256K X 16 BIT CMOS VIDEO RAM |
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| KM4-21L-13PN-MK2 | 制造商:Amphenol Corporation 功能描述:KM AUSTRALIAN PRODUCT - Bulk |
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