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參數(shù)資料
| 型號： | KM4216C258 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256K x 16 Bit CMOS Video RAM(256K x 16 位 CMOS視頻RAM) |
| 中文描述： | 256K × 16位的CMOS視頻RAM（256K × 16位的CMOS視頻內(nèi)存） |
| 文件頁數(shù)： | 16/41頁 |
| 文件大?。?/td> | 772K |
| 代理商： | KM4216C258 |
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KM4216C258
CMOS VIDEO RAM
Rev. 0.1 (Mar. 1998)
DEVICE OPERATIONS
( Continued)
Address Lines
: The row address is latched on the falling edge
of RAS. Since 8 columns are being written at a time, the mini-
mum increment required for the column address is eight.
Therefore, when the column address is latched at the falling
edge of CAS, the 3 LSBs, A
0
~ A
2
are ignored and only
bits(A
3
~A
8
) are used to define the location of the first bit out of
the eight to be written.
Data Lines
: On the falling edge of CAS, the data on the W
0
/
DQ
0
~ W
15
/DQ
15
pins provide column mask data. That is, for
each of the eight bits in all 16-bit planes, writing of Color Regis-
ter contents can be inhibited. For example, If W
0
/DQ
0
= 1 and
W
1
/DQ
1
= 0, then the Color Register contents will be written into
the first bit out of the 8, but the second remains unchanged.
Fig. 5 shows the correspondence of each data line to the col-
umn mask bits.
A masked Block Write cycle identical to a New/Old Masked
Write-per-bit cycle except that each of the 16-bit planes being
masked is operating on 8 column locations instead of one.
To perform a Masked Block Write cycle, both DSF and WB/WE
must be low at the falling edge of RAS. DSF must be high at the
falling edge of CAS. In new mask mode, Mask data is latched
into the device via the W
0
/DQ
0
~ W
15
/DQ
15
pins at the falling
edge of RAS and needs to be re-entered for every new RAS
cycle. And WB/WE must be low, DSF must be high on the falling
edge of CAS. In Old Mask Mode, I/O mask data will be provided
by the Mask Data Register.
X
X
X
X
X
X
X
X
X
1
X
1
1
1
X
X
X
0
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
1
X
1
1
1
X
X
X
0
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
1
X
1
1
1
X
X
0
1
0
1
1
1
0
0
0
1
1
0
1
1
0
1
0
1
0
1
1
0
0
1
W
0
/DQ
0
~ W
7
/DQ
7
Lower Byte
I/O Mask Data
Color Register
Mask Data
Column
X
X
X
X
X
X
X
X
X
1
X
1
1
1
X
X
X
0
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
1
X
1
1
1
X
X
X
0
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
1
X
1
1
1
X
X
0
1
0
1
1
1
0
0
0
1
1
0
1
1
0
1
0
1
0
1
1
0
0
1
W
8
/DQ
8
~ W
15
/DQ
15
Upper Byte
Memory Cell
X: Unchanged
8 Col. Memory Cell of A Row
4M VRAM BW Timing(Early Write)
RAS
CASL
CASU
WB/WE
W
0
/DQ
0~
W
15
/DQ
15
DT/OE
t
MS
t
MH
t
DS
t
DH
t
DS
t
DH
I/O
Mask
Address
Mask
Address
Mask
4M VRAM BW Timing(Late Write)
t
DS
t
DH
I/O
Mask
Address
Mask
Address
Mask
t
DS
t
DH
t
MS
t
MH
t
CWL
t
WCS
Enable
Enable
t
OEH
WPB
WPB
Figure 6. Block Write Example and Timing
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