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參數(shù)資料
| 型號： | K9T1G08U0M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128M x 8 Bits NAND Flash Memory |
| 中文描述： | 128M的x 8位NAND閃存 |
| 文件頁數(shù)： | 10/38頁 |
| 文件大?。?/td> | 888K |
| 代理商： | K9T1G08U0M |
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FLASH MEMORY
10
K9T1G08U0M
VALID BLOCK
Preliminary
CAPACITANCE
(
T
A
=25
°
C, V
CC
=3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
NOTE
:
1. The K9T1G08U0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycles.
3. Minimum 2,013 valid blocks are guaranteed for each contiguous 256Mb memory space.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
8,052
-
8,192
Blocks
AC TEST CONDITION
(K9T1G08U0M-XCB0 :TA=0 to 70
°
C, K9T1GXXU0M-XIB0:TA=-40 to 85
°
C)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
VccQ=3.0V+/-10% : 1 TTL GATE and CL= 50pF
VccQ=3.3V+/-10% : 1 TTL GATE and CL=100pF
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input (4 clocks)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input (4 clocks)
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
L
L
L
H
H
X
During Read (Busy)
X
X
X
X
X
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
(1)
-
200
500
μ
s
Dummy Busy Time for Multi Plane Program
t
DBSY
1
10
μ
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
1
cycle
Spare Array
-
-
2
cycle
Block Erase Time
NOTE
: 1.Typical program time is defined as the time within more than 50% of the whole pages are programmed at Vcc of 3.3V and 25
°
C
t
BERS
-
2
3
ms
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