參數(shù)資料
型號(hào): ISPPAC-POWR6AT6-01NN32I
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: In-System Programmable Power Supply Monitoring and Margining Controller
中文描述: 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝: 5 X 5 MM, LEAD FREE, QFN-32
文件頁(yè)數(shù): 30/34頁(yè)
文件大?。?/td> 906K
代理商: ISPPAC-POWR6AT6-01NN32I
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
30
Figure 27. ispPAC-POWR6AT6 ID Code
ispPAC-POWR6AT6 Specific Instructions
There are 15 unique instructions specified by Lattice for the ispPAC-POWR6AT6. These instructions are primarily
used to interface to the various user registers and the E
2
CMOS non-volatile memory. Additional instructions are
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 7.
BULK_ERASE
- This instruction will bulk erase the ispPAC-POWR6AT6. The action occurs at the second rising
edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode
(PROGRAM_ENABLE instruction).
PROGRAM_SECURITY
- This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction).
DISCHARGE
- This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR6AT6 for a read cycle.
PROGRAM_ENABLE
- This instruction enables the programming mode of the ispPAC-POWR6AT6.
IDCODE
- This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 28), to support reading out the identification code.
Figure 28. IDCODE Register
UES_READ
- This instruction both reads the E
2
CMOS bits in the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure 29), to support programming or reading of the user electronic
signature bits.
Figure 29. UES Register
UES_PROG
- This instruction will program the content of the UES Register into the UES E
2
CMOS memory. The
device must already be in programming mode (PROGRAM_ ENABLE instruction).
PROGRAM_DISABLE
- This instruction disables the programming mode of the ispPAC-POWR6A6. The Test-
Logic-Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR6A6.
XXXX / 0000 0001 1000 0000 / 0000 0100 001 / 1
MSB
LSB
Version
(4 bits)
E
2
Configured
Part Number
(16 bits)
0180h = ispPAC-POWR6AT6
JEDEC Manufacturer
Identity Code for
Lattice Semiconductor
(11 bits)
Constant 1
(1 bit)
per 1149.1-1990
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
27
Bit
28
Bit
29
Bit
30
Bit
31
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
11
Bit
12
Bit
13
Bit
14
Bit
15
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