參數(shù)資料
型號(hào)： ISPPAC-POWR6AT6-01NN32I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 電源管理
英文描述： In-System Programmable Power Supply Monitoring and Margining Controller
中文描述： 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝： 5 X 5 MM, LEAD FREE, QFN-32
文件頁(yè)數(shù)： 15/34頁(yè)
文件大?。?/td> 906K
代理商： ISPPAC-POWR6AT6-01NN32I
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
15
Figure 10. Digital Closed Loop Trim Operation
The closed loop trim cycle interval is programmable and is set by the update rate control register. The following
table lists the programmable update interval that can be selected by the update rate register.
Table 2. Output DAC Update Rate in Digital Closed Loop Mode
Closed Loop Trim Control Using the CLTENb Pin
There is a one-to-one relationship between the selected TrimCell and the corresponding VMON input for the closed
loop operation. For example, if TrimCell 3 is used to control the power supply in the closed loop trim mode, VMON3
must be used to monitor its output power supply voltage.
The CLTENb enable pin (active low) simultaneously starts the closed loop trimming process for all ispPAC-
POWR6AT6 trim outputs so configured. Behavior of individual trim output pins is defined using Lattice PAC-
Designer design software and stored in the ispPAC-POWR6AT6's non-volatile E
2
CMOS memory. In addition to a
closed-loop trim control option, two other configuration alternatives are available. The first stores a fixed, or static,
value for a given trim output in E
2
CMOS memory. The second enables dynamic trim adjustments to be made using
an external microcontroller via the ispPAC-POWR6AT6's I
2
C interface bus. Neither of these options is affected by
the CLTENb pin, however.
When the ispPAC-POWR6AT6's CLTENb pin goes low, closed-loop trimming is enabled. When CLTENb subse-
quently goes high, there is a brief delay after which closed-loop trimming is suspended. The delay is the time
required for ispPAC-POWR6AT6 control logic to complete a trim update cycle. Table 2 shows typical times for
update cycles based on which of four trim rates is initially chosen in PAC-Designer. When the trim process is
halted, it should also be noted the trim output DACs have constant voltage output levels (corresponding to their last
input code setting). This condition can be safely maintained indefinitely, but resuming closed-loop trimming (by tak-
ing CLTENb low) better insures power supplies remain precisely adjusted under all possible conditions. When re-
enabled, closed-loop trimming restarts where it left off. In this sense, the CLTENb pin can be thought of as a
“pause” control for closed-loop trim.
Update Rate
Control Value
00
01
10
11
Update
Interval
432 μs
1.06 ms
8.74 ms
16.9 ms
ADC
Three-State
DIGITAL
COMPARE
(+1/0/-1)
+/-1
SETPOI
N
T
(E
CMOS)
E
2
CMOS Registers
DAC Register 3
DAC Register 2
DAC Register 1
DAC Register 0
CHA
NN
EL
POLARITY
(E
2
CMOS)
TRIMx
R*
*Indicates resistor net
w
ork (see Fig
u
re
8
).
V
MO
N
x
TRIMI
N
DC-DC
CO
NV
ERTER
V
OUT
G
N
D
POWR6AT6
Closed Loop
Trim Register
DAC
TrimCell
UPDATE
RATE
CO
N
TROL
E
2
CMOS
DAC Register I
2
C
Profile 0 Mode
Control (E
CMOS)
Profile Control
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