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參數(shù)資料
| 型號： | ISPPAC-POWR6AT6-01NN32I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | In-System Programmable Power Supply Monitoring and Margining Controller |
| 中文描述： | 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, QFN-32 |
| 文件頁數(shù)： | 17/34頁 |
| 文件大?。?/td> | 906K |
| 代理商： | ISPPAC-POWR6AT6-01NN32I |
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
17
trim will begin and CLTLOCK/SMBA will only reassert when the trim process is complete. Contents of the I
2
C
cltlock_status register (0x00), however are not fully reset to initial conditions until the CLTLOCK/SMBA pin achieves
a reasserted state.
CAUTION: Issuing a RESET command through I
2
C or JTAG during the ispPAC-POWR6AT6 device operation,
results in the device aborting all operations and returning to the power-on reset state except for the one condition
mentioned above.
I
2
C/SMBUS Interface
I
2
C and SMBus are low-speed serial interface protocols designed to enable communications among a number of
devices on a circuit board. The ispPAC-POWR6AT6 supports a 7-bit addressing of the I
2
C communications proto-
col, as well as SMBTimeout and SMBAlert features of the SMBus, enabling it to easily integrated into many types
of modern power management systems. Figure 12 shows a typical I
2
C configuration, in which one or more ispPAC-
POWR6AT6s are slaved to a supervisory microcontroller. SDA is used to carry data signals, while SCL provides a
synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I
2
C address of the
POWR6AT6 is fully programmable through the JTAG port.
Figure 12. ispPAC-POWR6AT6 in I
2
C/SMBUS System
In both the I
2
C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The ispPAC-POWR6AT6 is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I
2
C bus is assigned a unique address. The ispPAC-POWR6AT6 implements the 7-bit
addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR6AT6 device by pro-
gramming through JTAG. When selecting a device address, one should note that several addresses are reserved
by the I
2
C and/or SMBus standards, and should not be assigned to ispPAC-POWR6AT6 devices to assure bus
compatibility. Table 3 lists these reserved addresses.
MICROPROCESSOR
(I
C MASTER)
ispPAC-POWR6AT6
(I
C SLAVE)
SDA
SDA
SDA
SCL
SCL
SCL
SCL/SMCLK (CLOCK)
SDA/SMDAT (DATA)
SMBALERT
OUT5/
SMBA
OUT5/
SMBA
To Other
I
C
Devices
INTERRUPT
V+
ispPAC-POWR6AT6
(I
C SLAVE)
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| ispPAC-POWR6AT6-01S32I | 功能描述:監(jiān)控電路 Prec Prog Pwr Supply Seq Mon IND RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ispPAC-POWR6AT6-01SN32I | 功能描述:監(jiān)控電路 Prec Prog Pwr Supply Seq Mon Trim IND RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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