參數(shù)資料
型號(hào)： ISPPAC-POWR6AT6-01NN32I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 電源管理
英文描述： In-System Programmable Power Supply Monitoring and Margining Controller
中文描述： 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32
封裝： 5 X 5 MM, LEAD FREE, QFN-32
文件頁(yè)數(shù)： 23/34頁(yè)
文件大小： 906K
代理商： ISPPAC-POWR6AT6-01NN32I
Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
23
Figure 20. Closed-Loop Trim Lock (CLTLOCK/SMBA) Signal Processing Logic Flow Diagram
The ispPAC-POWR6AT6 contains trim detection processing circuitry to signal when closed-loop trimming is com-
plete for selected trim output pins. This signal is output on the closed-loop control output pin (CLTLOCK/SMBA)
which has a open drain output and is normally asserted low (pull down). When all closed-loop trim output pins
reach a completion or trim “l(fā)ocked” condition, the CLTLOCK/SMBA output pin pulls low. Afterwards, the CLTLOCK/
SMBA pin also indicates when a trimming fault exists by de-asserting (going high). Finally, the CLTLOCK/SMBA pin
can be configured to work in conjunction with the SMBus Alert protocol to signal when trim lock has been achieved
or lost (see the section on SMBus Alert for details).
Figure 21 shows a simplified diagram of how the state of the CLTLOCK/SMBA output pin is generated. After closed
loop trimming is enabled, the CLTLOCK/SMBA signal processing logic examines the output result from the ADC
going to each TrimCell at the end of each trim update cycle. If it is determined that a trim lock condition exists for
that trim output pin, the trim lock signal is asserted. The status of an individual trim output can be read via the I
2
C
closed loop trim register (refer to Figure 15). Trim output pins not selected for closed-loop trim operation will auto-
matically indicate a trim locked condition.
Figure 21. Closed-Loop Trim Lock Output Pin (CLTLOCK/SMBA) Functionality
Next, an individual lock signal is OR'd with an E
2
CMOS mask bit specific to that trim output pin. There are six mask-
ing bits, one for each possible trim output pin. When set, masking bits effectively override the lock determination for
a particular trim output pin. The default setting for all mask bits is cleared (not set). Changes to the device configu-
ration mask bits can be made using PAC-Designer.
Start
R
u
ns
w
hen CLTE
Nb
pin is asserted.
V
mon-n ADC
meas
u
rement
Trim
Locked
Determine “Lock”
stat
u
s of Trim-n
Yes
N
o
Set “Lock” res
u
lt
for Trim-n
Clear “Lock” res
u
lt
for Trim-n
CLTLOCK/SMBA
E
2
Config
u
ration
Mask CLTLOCK/SMBA
Trim1-5
same as
b
elo
w
5
5
I
2
C CLTLOCK/SMBA Stat
u
s:
Trim1-6 (6-
b
its); 1 = Locked
C
P
6
lock = 1
1
I
2
C/
SMB
u
s
Control
Logic
1
0
E
2
Config
u
ration
Defa
u
lt = 0
Trim6
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