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| 型號(hào)： | ISPPAC-POWR6AT6-01NN32I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | In-System Programmable Power Supply Monitoring and Margining Controller |
| 中文描述： | 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, QFN-32 |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 906K |
| 代理商： | ISPPAC-POWR6AT6-01NN32I |
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Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
21
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-
sion. When the conversion is in process, the DONE bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I
2
C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-
mended that the I
2
C master load a second conversion command only after the completion of the current conversion
command (Waiting for the DONE bit to be set to 1). An alternative would be to wait for a minimum specified time
(see Tconvert value in the specifications) and disregard checking the DONE bit.
Note that if the I
2
C clock rate falls below 50kHz (see F
I2C
note in specifications), the only way to insure a valid ADC
conversion is to wait the minimum specified time (Tconvert), as the operation of the DONE bit at clock rates lower
than that cannot be guaranteed. In other words, if the I
2
C clock rate is less than 50kHz, the DONE bit may or may
not assert even when a valid conversion result is available. Erroneous ADC readout results are also possible when-
ever the I
2
C clock is less than 50kHz and a second ADC convert is commanded before a full T
CONVERT
time period
has elapsed. Under these conditions, it is still possible to obtain valid results for the second conversion by reading
out the ADC low and high byte results twice in succession (read ADC_VALUE_LOW, read ADC_VALUE_HIGH,
then repeating the low and high byte reads). Only the second ADC readout value is reliably valid, however.
To insure every ADC conversion result is valid, preferred operation is to clock I
2
C at more than 50kHz and verify
DONE bit status or wait for the full T
CONVERT
time period between subsequent ADC convert commands. If an I
2
C
request is placed before the current conversion is complete, the DONE bit will be set to 1 only after the second
request is complete.
The UES word may also be read through the I
2
C interface, with the register mapping shown in Figure 17.
Figure 17. I
2
C Register Mapping for UES Bits
The I
2
C interface also provides the ability to initiate reset operations. The ispPAC-POWR6AT6 may be reset by issu-
ing a write of any value to the I
2
C RESET register (Figure 18). Refer to the RESET Command via JTAG or I
2
C sec-
tion of this data sheet for further information.
UES7
UES6
UES5
UES4
UES3
UES2
UES1
UES0
b7
b0
0x04 - UES_BYTE0
(Read Only)
b6
b5
b4
b3
b2
b1
UES15
UES14
UES13
UES12
UES11
UES10
UES9
UES8
b7
b0
0x05 - UES_BYTE1
(Read Only)
b6
b5
b4
b3
b2
b1
UES23
UES22
UES21
UES20
UES19
UES18
UES17
UES16
b7
b0
0x06 - UES_BYTE2
(Read Only)
b6
b5
b4
b3
b2
b1
UES31
UES30
UES29
UES28
UES27
UES26
UES25
UES24
b7
b0
0x07 - UES_BYTE3
(Read Only)
b6
b5
b4
b3
b2
b1
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