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參數(shù)資料
| 型號： | ISPPAC-POWR1014A |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| 中文描述： | 在系統(tǒng)可編程電源監(jiān)控器，復位發(fā)生器和排序控制器 |
| 文件頁數(shù)： | 39/45頁 |
| 文件大?。?/td> | 999K |
| 代理商： | ISPPAC-POWR1014A |
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Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
39
CFG_ADDRESS
– This instruction is used to set the address of the CFG array for subsequent program or read
operations. This instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_DATA_SHIFT
– This instruction is used to shift data into the CFG register prior to programming or reading.
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_ERASE
– This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK
in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_E
N
ABLE instruction).
This instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_PROGRAM
– This instruction programs the selected CFG array column. This specific column is preselected
by using CFG_ADDRESS instruction. The programming occurs at the second rising edge of the TCK in Run-Test-
Idle JTAG state. The device must already be in programming mode (PROGRAM_E
N
ABLE instruction). This
instruction also forces the outputs into the OUTPUTS_HIGHZ.
CFG_VERIFY
– This instruction is used to read the content of the selected CFG array column. This specific column
is preselected by using CFG_ADDRESS instruction. This instruction also forces the outputs into the
OUTPUTS_HIGHZ.
BULK_ERASE
– This instruction will bulk erase all E
2
CMOS bits (CFG, PLD, UES, and ESF) in the ispPAC-
POWR1014/A. The device must already be in programming mode (PROGRAM_E
N
ABLE instruction). This instruc-
tion also forces the outputs into the OUTPUTS_HIGHZ.
OUTPUTS_HIGHZ
– This instruction turns off all of the open-drain output transistors. Pins that are programmed as
FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register
JTAG state.
PROGRAM_ENABLE
– This instruction enables the programming mode of the ispPAC-POWR1014/A. This
instruction also forces the outputs into the OUTPUTS_HIGHZ.
IDCODE
– This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 32), to support reading out the identification code.
Figure 32. IDCODE Register
PROGRAM_DISABLE
– This instruction disables the programming mode of the ispPAC-POWR1014/A. The Test-
Logic-Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR1014/A.
UES_READ
– This instruction both reads the E
2
CMOS bits into the UES register and places the UES register
between the TDI and TDO pins (as shown in Figure 29), to support programming or reading of the user electronic
signature bits.
Figure 33. UES Register
UES_PROGRAM
– This instruction will program the content of the UES Register into the UES E
2
CMOS memory.
The device must already be in programming mode (PROGRAM_E
N
ABLE instruction). This instruction also forces
the outputs into the OUTPUTS_HIGHZ.
ERASE_DONE_BIT
– This instruction clears the 'Done' bit, which prevents the ispPAC-POWR1014/A sequence
from starting.
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
27
Bit
28
Bit
29
Bit
30
Bit
31
TDO
Bit
0
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
8
Bit
9
Bit
10
Bit
11
Bit
12
Bit
13
Bit
14
Bit
15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-POWR1014A-01T48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR1014A-01TN48I | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| ISPPAC-POWR6AT6-01N32I | In-System Programmable Power Supply Monitoring and Margining Controller |
| ISPPAC-POWR6AT6-01NN32I | In-System Programmable Power Supply Monitoring and Margining Controller |
| ISPPAC10 | In-System Programmable Analog Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACPOWR1014A01T48I | 制造商:Lattice Semiconductor Corporation 功能描述:Volt Supervisor Sequencer/Monitor 48-Pin TQFP |
| ispPAC-POWR1014A-01T48I | 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISPPAC-POWR1014A-01TN148I | 制造商:Lattice Semiconductor Corporation 功能描述:IC POWER SUPP MONITOR SMD TQFP48 制造商:Lattice Semiconductor Corporation 功能描述:IC, POWER SUPP MONITOR, SMD, TQFP48 |
| ispPAC-POWR1014A-01TN48I | 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISPPACPOWR1014A01TN48IAG6 | 制造商:Lattice Semiconductor Corporation 功能描述: |
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