參數(shù)資料
型號(hào)： ISPPAC-POWR1014A
廠商： Lattice Semiconductor Corporation
英文描述： In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述： 在系統(tǒng)可編程電源監(jiān)控器，復(fù)位發(fā)生器和排序控制器
文件頁(yè)數(shù)： 37/45頁(yè)
文件大?。?/td> 999K
代理商： ISPPAC-POWR1014A
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
37
Table 11. ispPAC-POWR1014/A TAP Instruction Table
BYPASS
is one of the three required instructions. It selects the Bypass Register to be connected between TDI and
TDO and allows serial data to be transferred through the device without affecting the operation of the ispPAC-
POWR1014/A. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (11111111).
The required
SAMPLE/PRELOAD
instruction dictates the Boundary-Scan Register be connected between TDI
and TDO. The ispPAC-POWR1014/A has no boundary scan register, so for compatibility it defaults to the BYPASS
mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in
Table 11.
The
EXTEST
(external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
ispPAC-POWR1014/A has no boundary scan logic, the device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (00000000).
Instruction
Command
Code
0000 0011
1111 1111
0001 0100
0010 0100
0000 0000
0001 0110
0001 1000
00011100
0001 1110
0010 1111
0001 0101
0000 1001
Comments
BULK_ERASE
BYPASS
DISCHARGE
ERASE_DO
N
E_BIT
EXTEST
IDCODE
OUTPUTS_HIGHZ
SAMPLE/PRELOAD
PROGRAM_DISABLE
PROGRAM_DO
N
E_BIT
PROGRAM_E
N
ABLE
PROGRAM_SECURITY
Bulk erase device
Bypass - connect TDO to TDI
Fast VPP discharge
Erases ‘Done’ bit only
Bypass - connect TDO to TDI
Read contents of manufacturer ID code (32 bits)
Force all outputs to High-Z state, FET outputs pulled low
Sample/Preload. Default to bypass.
Disable program mode
Programs the Done bit
Enable program mode
Program security fuse
Resets device (refer to the RESETb Signal, RESET Command via
JTAG or I
2
C section of this data sheet)
Reset the JTAG bit associated with I
N
1 pin to 0
Set the JTAG bit associated with I
N
1 pin to 1
Select non-PLD address register
N
on-PLD data shift
ERASE Just the
N
on PLD configuration
N
on-PLD program
VRIFY non-PLD fusemap data
PLD_Address register (109 bits)
PLD_Data register (123 Bits)
Initialize the address register for auto increment
Program column register to E
2
and auto increment address register
Program PLD data register to E
2
Verifies PLD column data
Load column register from E
2
and auto increment address register
Program UES bits into E
2
Read contents of UES register from E
2
(32 bits)
RESET
0010 0010
I
N
1_RESET_JTAG_BIT
I
N
1_SET_JTAG_BIT
CFG_ADDRESS
CFG_DATA_SHIFT
CFG_ERASE
CFG_PROGRAM
CFG_VERIFY
PLD_ADDRESS_SHIFT
PLD_DATA_SHIFT
PLD_I
N
IT_ADDR_FOR_PROG_I
N
CR
PLD_PROG_I
N
CR
PLD_PROGRAM
PLD_VERIFY
PLD_VERIFY_I
N
CR
UES_PROGRAM
UES_READ
0001 0010
0001 0011
0010 1011
0010 1101
0010 1001
0010 1110
0010 1000
0000 0001
0000 0010
0010 0001
0010 0111
0000 0111
0000 1010
0010 1010
0001 1010
0001 0111
相關(guān)PDF資料
PDF描述
ISPPAC-POWR1014A-01T48I In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ISPPAC-POWR1014A-01TN48I In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
ISPPAC-POWR6AT6-01N32I In-System Programmable Power Supply Monitoring and Margining Controller
ISPPAC-POWR6AT6-01NN32I In-System Programmable Power Supply Monitoring and Margining Controller
ISPPAC10 In-System Programmable Analog Circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACPOWR1014A01T48I 制造商:Lattice Semiconductor Corporation 功能描述:Volt Supervisor Sequencer/Monitor 48-Pin TQFP
ispPAC-POWR1014A-01T48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPAC-POWR1014A-01TN148I 制造商:Lattice Semiconductor Corporation 功能描述:IC POWER SUPP MONITOR SMD TQFP48 制造商:Lattice Semiconductor Corporation 功能描述:IC, POWER SUPP MONITOR, SMD, TQFP48
ispPAC-POWR1014A-01TN48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPACPOWR1014A01TN48IAG6 制造商:Lattice Semiconductor Corporation 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*