參數(shù)資料
型號: ISPPAC-POWR1014A
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述: 在系統(tǒng)可編程電源監(jiān)控器,復(fù)位發(fā)生器和排序控制器
文件頁數(shù): 17/45頁
文件大?。?/td> 999K
代理商: ISPPAC-POWR1014A
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
17
Table 3. Comparator Hysteresis vs. Trip-Point
The window control section of the voltage monitor circuit is an A
N
D gate (with inputs: an inverted COMPA “A
N
Ded”
with COMPB signal) and a multiplexer that supports the ability to develop a ‘window’ function without using any of
the PLD’s resources. Through the use of the multiplexer, voltage monitor’s ‘A’ output may be set to report either the
status of the ‘A’ comparator, or the window function of both comparator outputs. The voltage monitor’s ‘A’ output
indicates whether the input signal is between or outside the two comparator thresholds.
Important:
This windowing
function is only valid in cases where the threshold of the ‘A’ comparator is set to a value higher than that of the ‘B’
comparator. Table 4 shows the operation of window function logic.
Table 4. Voltage Monitor Windowing Logic
N
ote that when the ‘A’ output of the voltage monitor circuit is set to windowing mode, the ‘B’ output continues to
monitor the output of the ‘B’ comparator. This can be useful in that the ‘B’ output can be used to augment the win-
dowing function by determining if the input is above or below the windowing range.
The third section in the ispPAC-POWR1014/A’s input voltage monitor is a digital filter. When enabled, the compara-
tor output will be delayed by a filter time constant of 64 μs, and is especially useful for reducing the possibility of
false triggering from noise that may be present on the voltages being monitored. When the filter is disabled, the
comparator output will be delayed by 16μs. In both cases, enabled or disabled, the filters also provide synchroniza-
tion of the input signals to the PLD clock. This synchronous sampling feature effectively eliminates the possibility of
race conditions from occurring in any subsequent logic that is implemented in the ispPAC-POWR1014/A’s internal
PLD logic.
The comparator status can be read from the I
2
C interface (ispPAC-POWR1014A only). For details on the I
2
C inter-
face, please refer to the I
2
C/SMBUS Interface section of this data sheet.
Trip-point Range (V)
Low Limit
0.672
0.800
0.952
1.133
1.346
1.603
1.908
2.267
2.691
3.199
4.105
4.889
75 mV
Hysteresis (mV)
8
10
12
14
17
20
24
28
34
40
51
61
0 (Disabled)
High Limit
0.806
0.960
1.143
1.360
1.612
1.923
2.290
2.719
3.223
3.839
4.926
5.867
Input Voltage
Comp A
0
0
1
Comp B
0
1
1
Window
(B and Not A)
0
1
0
Comment
V
I
N
< Trip-point B < Trip-point A
Trip-point B < V
I
N
< Trip-point A
Trip-point B < Trip-point A < V
I
N
Outside window, low
Inside window
Outside window, high
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ISPPACPOWR1014A01TN48IAG6 制造商:Lattice Semiconductor Corporation 功能描述: