參數(shù)資料
型號(hào): ISPPAC-POWR1014A
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述: 在系統(tǒng)可編程電源監(jiān)控器,復(fù)位發(fā)生器和排序控制器
文件頁數(shù): 26/45頁
文件大小: 999K
代理商: ISPPAC-POWR1014A
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
26
Figure 18. ADC Interface Registers
To perform an A/D conversion, one must set the input attenuator and channel selector. Two input ranges may be
set using the attenuator, 0 - 2.048V and 0 - 6.144V. Table 8 shows the input attenuator settings.
Table 8. ADC Input Attenuator Control
The input selector may be set to monitor any one of the ten VMO
N
inputs, the VCCA input, or the VCCI
N
P input.
Table 9 shows the codes associated with each input selection.
Table 9. V
MON
Address Selection Table
Writing a value to the ADC_MUX register to set the input attenuator and selector will automatically initiate a conver-
sion. When the conversion is in process, the DO
N
E bit (ADC_VALUE_LOW.0) will be reset to 0. When the conver-
sion is complete, this bit will be set to 1. When the conversion is complete, the result may be read out of the ADC by
performing two I
2
C read operations; one for ADC_VALUE_LOW, and one for ADC_VALUE_HIGH. It is recom-
mended that the I
2
C master load a second conversion command only after the completion of the current conversion
ATTEN (ADC_MUX.4)
0
1
Resolution
2mV
6mV
Full-Scale Range
2.048 V
6.144 V
Select Word
SEL2
(ADC_MUX.2)
0
0
0
0
1
1
1
1
0
0
1
1
Input Channel
VMO
N
1
VMO
N
2
VMO
N
3
VMO
N
4
VMO
N
5
VMO
N
6
VMO
N
7
VMO
N
8
VMO
N
9
VMO
N
10
VCCA
VCCI
N
P
SEL3
(ADC_MUX.3)
0
0
0
0
0
0
0
0
1
1
1
1
SEL1
(ADC_MUX.1)
0
0
1
1
0
0
1
1
0
0
0
0
SEL0
(ADC_MUX.0)
0
1
0
1
0
1
0
1
0
1
0
1
D3
D2
D1
D0
1
1
1
DONE
b7
b0
0x07 - ADC_VALUE_LOW
(Read Only)
b6
b5
b4
b3
b2
b1
D11
D10
D9
D8
D7
D6
D5
D4
b7
b0
0x08 - ADC_VALUE_HIGH
(Read Only)
b6
b5
b4
b3
b2
b1
X
X
X
ATTEN
SEL3
SEL2
SEL1
SEL0
b7
b0
0x09 - ADC_MUX (Read/Write)
b6
b5
b4
b3
b2
b1
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