參數(shù)資料
型號(hào): ISPPAC-POWR1014A
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述: 在系統(tǒng)可編程電源監(jiān)控器,復(fù)位發(fā)生器和排序控制器
文件頁(yè)數(shù): 22/45頁(yè)
文件大小: 999K
代理商: ISPPAC-POWR1014A
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
22
Figure 13. Basic Function Diagram for an Output in High Voltage MOSFET Gate Driver Mode
Figure 13 shows the HVOUT circuitry when programmed as a FET driver. In this mode the output either sources
current from a charge pump or sinks current. The maximum voltage that the output level at the pin will rise to is also
programmable between 6V and 10V. The maximum voltage levels that are required depend on the gate-to-source
threshold of the FET being driven and the power supply voltage being switched. The maximum voltage level needs
to be sufficient to bias the gate-to-source threshold on and also accommodate the load voltage at the FET’s
source, since the source pin of the FET to provide a wide range of ramp rates is tied to the supply of the target
board. When the HVOUT pin is sourcing current, charging a FET gate, the source current is programmable
between 12.5μA and 100μA. When the driver is turned to the off state, the driver will sink current to ground, and
this sink current is also programmable between 3000μA and 100μA to control the turn-off rate.
Programmable Output Voltage Levels for HVOUT1- HVOUT2
There are three selectable steps for the output voltage of the FET drivers when in FET driver mode. The voltage
that the pin is capable of driving to can be programmed from 6V to 10V in 2V steps.
RESETb Signal, RESET Command via JTAG or I
2
C
Activating the RESETb signal (Logic 0 applied to the RESETb pin) or issuing a reset instruction via JTAG, or with
the ispPAC-POWR1014A, I
2
C will force the outputs to the following states independent of how these outputs have
been configured in the PI
N
S window:
OUT3-14 will go high-impedance.
HVOUT pins programmed for open drain operation will go high-impedance.
HVOUT pins programmed for FET driver mode operation will pull down.
At the conclusion of the RESET event, these outputs will go to the states defined by the PI
N
S window, and if a
sequence has been programmed into the device, it will be re-started at the first step. The analog calibration will be
re-done and consequently, the VMO
N
s, and ADCs will not be operational until 500 microseconds (max.) after the
conclusion of the RESET event.
CAUTION: Activating the RESETb signal or issuing a RESET command through I2C or JTAG during the ispPAC-
POWR1014/A device operation, results in the device aborting all operations and returning to the power-on reset
state. The status of the power supplies which are being enabled by the ispPAC-POWR1014/A will be determined by
the state of the outputs shown above.
I
SOURCE
(12.5 to 100
μ
A)
I
SINK
(100 to 500
μ
A)
+Fast T
u
rn-off
(3000
μ
A)
Charge P
u
mp
(6 to 10
V
)
Inp
u
t
S
u
pply
Load
H
V
OUTx
Pin
Digital Control
from PLD
Digital Control from I
2
C Register
(ispPAC-PO
W
R1014A Only)
+
-
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ISPPACPOWR1014A01TN48IAG6 制造商:Lattice Semiconductor Corporation 功能描述: