參數(shù)資料
型號(hào)： ISPPAC-POWR1014A
廠商： Lattice Semiconductor Corporation
英文描述： In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
中文描述： 在系統(tǒng)可編程電源監(jiān)控器，復(fù)位發(fā)生器和排序控制器
文件頁(yè)數(shù)： 36/45頁(yè)
文件大?。?/td> 999K
代理商： ISPPAC-POWR1014A
Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
36
Figure 30. TAP States
When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state
and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction shift
is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruc-
tion shift is performed. The states of the Data and Instruction Register blocks are identical to each other differing
only in their entry points. When either block is entered, the first action is a capture operation. For the Data Regis-
ters, the Capture-DR state is very simple: it captures (parallel loads) data onto the selected serial data path (previ-
ously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load
the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior to a
Shift-DR operation. This, in conjunction with mandated bit codes, allows a “blind” interrogation of any device in a
compliant IEEE 1149.1 serial chain. From the Capture state, the TAP transitions to either the Shift or Exit1 state.
N
ormally the Shift state follows the Capture state so that test data or status information can be shifted out or new
data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update
states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data
through either the Data or Instruction Register while an external operation is performed. From the Pause state,
shifting can resume by reentering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle
state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry
into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed,
erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions. Any additional instructions are left exclusively for the manu-
facturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only
the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec-
tively). The ispPAC-POWR1014/A contains the required minimum instruction set as well as one from the optional
instruction set. In addition, there are several proprietary instructions that allow the device to be configured and ver-
ified. Table 11 lists the instructions supported by the ispPAC-POWR1014/A JTAG Test Access Port (TAP) controller:
Test-Logic-Rst
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
Capture-DR
Capture-IR
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
Pause-DR
Pause-IR
Exit2-DR
Exit2-IR
Update-DR
Update-IR
1
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
0
N
ote: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACPOWR1014A01T48I 制造商:Lattice Semiconductor Corporation 功能描述:Volt Supervisor Sequencer/Monitor 48-Pin TQFP
ispPAC-POWR1014A-01T48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPAC-POWR1014A-01TN148I 制造商:Lattice Semiconductor Corporation 功能描述:IC POWER SUPP MONITOR SMD TQFP48 制造商:Lattice Semiconductor Corporation 功能描述:IC, POWER SUPP MONITOR, SMD, TQFP48
ispPAC-POWR1014A-01TN48I 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel
ISPPACPOWR1014A01TN48IAG6 制造商:Lattice Semiconductor Corporation 功能描述:
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