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參數(shù)資料
| 型號： | HT82A851R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | USB Audio MCU |
| 中文描述： | USB音頻控制器 |
| 文件頁數(shù)： | 9/43頁 |
| 文件大?。?/td> | 304K |
| 代理商： | HT82A851R |
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HT82A851R
Rev. 1.20
9
June 15, 2007
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain
interrupt requires servicing within the service routine,
the EMI bit and the corresponding bit of the INTC0 or
INTC1 may be set to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the stack
pointer is decremented. If immediate service is desired,
the stack must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
The
USB
interrupts are triggered by the following
USB
events and the related interrupt request flag (USBF; bit
4 of the INTC0) will be set.
Accessing the corresponding
USB
FIFO from the PC
The
USB
suspend signal from the PC
The
USB
resume signal from the PC
USB Reset signal
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag (USBF) and
EMI bits will be cleared to disable other interrupts.
When the PC Host accesses the FIFO of the
HT82A851R, the corresponding request bit of the USR
is set, and a USB interrupt is triggered. So the user can
easily determine which FIFO has been accessed. When
the interrupt has been served, the corresponding bit
should be cleared by firmware. When the HT82A851R
receives a USB Suspend signal from the Host PC, the
suspend line (bit0 of USC) of the HT82A851R is set and
a USB interrupt is also triggered.
Also when the HT82A851R receives a Resume signal
from the Host PC, the resume line (bit3 of USC) of the
HT82A851R is set and a USB interrupt is triggered.
The internal Timer/Event Counter 0 interrupt is
initialized by setting the Timer/Event Counter 0 interrupt
request flag (bit 5 of INTC0), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further
interrupts.
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
USBF
USB interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
Unused bit, read as 0
INTC0 (0BH) Register
Bit No.
Label
Function
0
EPLAYI
Play interrupt (1=enable; 0=disable)
1
ESII
Control Serial interface interrupt (1=enable; 0=disable)
2
RECI
Record interrupt (1=enable; 0=disable)
3, 7
Unused bit, read as 0
4
PLAYF
Play interrupt request flag (1=active; 0=inactive)
5
SIF
Serial interface interrupt request flag (1=active; 0=inactive)
6
RECF
Record interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register
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