參數(shù)資料
型號(hào)： HT82A851R
廠商： Holtek Semiconductor Inc.
英文描述： USB Audio MCU
中文描述： USB音頻控制器
文件頁(yè)數(shù)： 24/43頁(yè)
文件大小： 304K
代理商： HT82A851R
HT82A851R
Rev. 1.20
24
June 15, 2007
SBDR: Serial bus data register
Data written to SBDR
Data read from SBDR
write data to the TXRX buffer only
read from SBDR only
Operating Mode description:
Master transmitter: clock sending and data I/O started by writing to SBDR
Master clock sending started by writing to SBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception
Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Serial Interface Operation:
Label
Functions
Master
Select CKS and select M1,M0 = 00, 01, 10
Select CSEN, MLS (same as slave)
Set SBEN
Writing data to SBDR
to step 5
(SIO internal operation
into the TXRX buffer
Check WCOL; WCOL = 1
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
data is stored in the TXRX buffer
data stored in the TXRX buffer, and the SDI data is shifted
data transferred, data in the TXRX buffer is latched into SBDR)
clear WCOL and go to step 4; WCOL = 0
output CLK (and SCS) signals
go
go to step 6
Slavehans
CKS don t care and select M1, M0 = 11
Select CSEN, MLS (same as master)
Set SBEN
Writing data to SBDR
SCS): CLK
go to step 5
TXRX buffer and SDI data is shifted into the TXRX buffer
buffer is latched into SBDR)
Check WCOL; WCOL = 1
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
data is store in the TXRX buffer
(SIO internal operations
waiting for master clock signal (and
CLK (SCS) received
data transferred, data in the TXRX
output data in
clear WCOL, go to step 4; WCOL = 0
go to step 6
WCOL:master/slavemode,setifwritingtoSBDRwhendataistransferring(transmittingorreceiving)andthiswriting
will be ignored. The WCOL function can be enabled/disabled by a software option (SIO_WCOL bit of MODE_CTRL
register). WCOL is set by SIO and cleared by the user.
Data transmission and reception will continue to operated when the MCU enters the power-down mode.
CPOLisusedtoselecttheclockpolarityofCLKandisasoftwareoption(SIO_CPOLbitofMODE_CTRLregister).
MLS: MSB or LSB first selection
CSEN: chip select function enable/disable, CSEN = 1
SCS signal before the CLK signal and slave data transferring should be disabled(enabled) before(after) SCS signal
received. CSEN = 0, SCS signal is not needed, SCS pin (master and slave) should be floating.
SCS signal function is active. The master should output a
CSEN: CSEN software option (SIO_CSEN bit of MODE_CTRL register) is used to enable/disable software CSEN
function. If CSEN software option is disable, software CSEN always disabled. If CSEN software option is enabled,
software CSEN function can be used.
SBEN = 1
CLK = output 1/0 (dependent on CPOL software option), slave CLK = floating
serial bus standby; SCS (CSEN = 1) = 1; SCS = floating (CSEN = 0); SDI = floating; SDO = 1; master
SBEN = 0
serial bus disable; SCS = SDI = SDO = CLK = floating
TRF is set by SIO and cleared by the user. When the data is transferring (transmission and reception) is complete,
TRF is set to generate SBI (serial bus interrupt).
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