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參數(shù)資料
| 型號： | HT82A851R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | USB Audio MCU |
| 中文描述： | USB音頻控制器 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大小： | 304K |
| 代理商： | HT82A851R |
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HT82A851R
Rev. 1.20
15
June 15, 2007
If the timer/event counter is turned OFF, writing data to
the timer/event counter preload register will also reload
the data into the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event
counter preload register. The timer/event counter keeps
operating until an overflow occurs.
When the timer/event counter is read, the clock is
blocked to avoid errors, which may result in a counting
error. Blocking of the clock should be taken into account
by the programmer.
Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, labeled from PA, PC which are mapped
to the data memory of [12H], [16H] respectively. All of
these I/O ports can be used for input and output
operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction MOV A,[m] (m=12H, 16H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PCC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt trigger input with or
without pull-high resistor structures can be reconfigured
dynamically (i.e. on-the-fly) under software control. To
function as an input, the corresponding latch of the
control register must write 1 . The input source also
depends on the control register. If the control register bit
is 1 the input will read the pad state. If the control
register bit is 0 the contents of the latches will move to
the internal bus. The latter is possible in the
Read-modify-write
CMOS configurations can be selected. These control
registers are mapped to locations 13H, 17H.
instruction. For output function,
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (depending on the pull-high
options). Each bit of these input/output latches can be
set or cleared by SET [m].i and CLR [m].i (m=12H,
16H) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
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) (
'
)
&
%
"
%
&
8 % ,
( ' B
%
&
%
% ,
&
B
# & C
%
#
/
( 0
8 % ,
( ' B
%
4
) ( 6
#
Timer/Event Counter 0/1
Bit No.
Label
Function
0~2, 5
Unused bit, read as 0
3
TE
Defines the TMR active edge of the timer/event counter
In Event counter mode (TM1, TM0)=(0, 1):
1=count on falling edge;
0=count on rising edge
In Pulse width measurement mode (TM1, TM0)=(1, 1):
1=start counting on the rising edge, stop on the falling edge;
0=start counting on the falling edge, stop on the rising edge
4
TON
Enable/disable the timer counting (0=disable; 1=enable)
6
7
TM0
TM1
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C (0EH), TMR1C (11H) Register
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