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參數(shù)資料
| 型號(hào)： | HT82A851R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | USB Audio MCU |
| 中文描述： | USB音頻控制器 |
| 文件頁數(shù)： | 26/43頁 |
| 文件大?。?/td> | 304K |
| 代理商： | HT82A851R |
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HT82A851R
Rev. 1.20
26
June 15, 2007
Label
Functions
WCOL
Set by SIO cleared by users
CESN
Enable or disable device selection function pin
Master mode: 1/0=with/without SCS output control
Slave mode: 1/0= with/without SCS input control
SBEN
Enable or disable serial bus (0= initialize all status flags)
When SBEN=0, all status flags should be initialized
When SBEN=0, all SIO related function pins should stay in a floating state
TRF
1= data transmitted or received
0= data is transmitting or still not received
If the clock polarity set to rising edge (SIO_CPOL=1), the serial clock timing will follow CLK, otherwise (SIO_CPOL=0)
CLK is the serial clock timing.
Mode Control
The MODE_CTRL register is used to control SPI function.
Bit No.
Label
Functions
0~2
Reserved
3
PLAY_MODE
Play mode control
1= 8kHz/16-bit
0= 48kHz/16-bit (default)
4
SIO_CPOL
There are three bits used to control the mode of SPI operation.
1= clock polarity rising edge
0= clock polarity falling edge (default)
5
SIO_WCOL
1= WCOL bit of SBCR register enable
0= WCOL bit of SBCR register disable (default)
6
SIO_CSEN
1= CSEN bit of SBCR register enable
0= CSEN bit of SBCR register disable (Default)
7
Undefined bit, read as 0
MODE_CTRL (34H) Register
SPI Usage Example
SPI_Test:
clr
set
clr
;Master Mode, SCLK=fSIO
clr
M1
clr
M0
;--------------
clr
CKS
clr
TRF
clr
TRF_INT
set
MLS
set
CSEN
set
SBEN
if POLLING_MODE
clr
ESII
;WRITE INTO WRITE ENABLE INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF
jmp
$0
clr
TRF
else
UCC.@UCC_SYSCLK
SIO_CSEN
SIO_CPOL
;12MHz SYSCLK
;SPI Chip Select Function Enable
;falling edge change data
;fSIO=f
SYS
/2
;clear TRF flag
;clear Interrupt SPI flag
;MSB shift first
;Chip Select Enable
;SPI Enable, SCS will go low
;SPI Interrupt Disable
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