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參數(shù)資料

型號(hào)：	HT82A851R
廠商：	Holtek Semiconductor Inc.
英文描述：	USB Audio MCU
中文描述：	USB音頻控制器
文件頁(yè)數(shù)：	14/43頁(yè)
文件大小：	304K
代理商：	HT82A851R

HT82A851R

Rev. 1.20

June 15, 2007

Reset

(Power On)

WDT

Time-out

(Normal

Operation)

RES Reset

(Normal

Operation)

RES Reset

(HALT)

WDT

Time-Out

(HALT)*

USB Reset

(Normal)

USB Reset

(HALT)

PFDC

0000 0000

0uuu 0000

PFDD

0000 0000

0uuu 0000

MODE_CTRL

0000 0000

0000 0uuu

SBCR

0110 0000

uuuu uuuu

SBDR

uuuu uuuu

RECORD_IN_L

0000 0000

uuuu uuuu

RECORD_IN_H

0000 0000

uuuu uuuu

PLAY_DATAL_L

0000 0000

uuuu uuuu

PLAY_DATAL_H

0000 0000

uuuu uuuu

PLAY_DATAR_L

0000 0000

uuuu uuuu

PLAY_DATAR_H

0000 0000

uuuu uuuu

Note:

* stands for warm reset

u stands for unchanged

x stands for unknown

- stands for undefined

Timer/Event Counter

Two timer/event counters are implemented in the

microcontroller. Each timer contains a 16-bit

programmable count-up counter whose clock may be

sourced from an external or internal clock source. The

internal clock source comes from f

SYS

/4. The external

clock input allows external events to be counted, time

intervals or pulse widths to be measured, or to generate

an accurate time base. There are three registers related

toTimer/EventCounter0,TMR0H,TMR0LandTMR0C,

and another three related to Timer/Event Counter 1,

TMR1H, TMR1L and TMR1C. When writing data to the

TMR0Land TMR1Lregisters, note that the data will only

be written into a lower-order byte buffer. The data will

not be actually written into the

registers until a write operation to the TMR0H and

TMR1H registers is implemented. Reading the TMR0L

and TMR1L registers will read the contents of the

lower-order byte buffer. The TMR0C and TMR1C

registers are the Timer/Event Counter control registers,

which define the operating mode, the count enable or

disable and the active edge.

TMR0L and TMR1L

The TM0 and TM1 bits define the operation mode. The

event count mode is used to count external events,

which means that the clock source is sourced from the

external TMR0 or TMR1 pin. The timer mode functions

as a normal timer with the clock source coming from the

internal clock. Finally, the pulse width measurement

mode can be used to count the high level or low level

duration of an external signal on pins TMR0 or TMR1,

whose counting is based on the internal clock source.

In the event count or timer mode, the timer/event

counter starts counting from the current contents in the

timer/event counter and ends at

FFFFH

. Once an

overflow occurs, the counter is reloaded from the

timer/event counter preload register, and generates an

interrupt request flag (T0F; bit 5 of INTC0, or T1F; bit 6

of INTC0). In the pulse width measurement mode with

the values of the TON and TE bits equal to 1, after the

TMR0 or TMR1 pin has received a transient from low to

high, or high to low if the TE bit is 0 , it will start counting

until the TMR0 or TMR1 pin returns to its original level

and resets the TON bit. The measured result remains in

the timer/event counter even if the activated transient

occurs again. Therefore, only 1-cycle measurement is

made. Not until the TON bit is again set can the cycle

measurement re-function. In this operational mode, the

timer/event counter begins counting not according to

the logic level but to the transient edges. In the case of

counter overflows, the counter is reloaded from the

timer/event counter register and issues an interrupt

request, as in the other two modes, i.e., event and timer

modes.

To enable a count operation, the Timer ON bit (TON; bit

4 of TMR0C or TMR1C) should be set to 1. In the pulse

width measurement mode, TON is automatically

cleared after the measurement cycle is completed. But

in the other two modes, the TON bit can only be reset by

instructions. A Timer/Event Counter overflow is one of

the wake-up sources. No matter what the operational

mode is, writing a 0 to ET0I or ET1I disables the related

interrupt service.

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