參數(shù)資料
型號(hào): HSP50210
廠商: HARRIS SEMICONDUCTOR
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop(數(shù)字Costas鎖相環(huán))
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁(yè)數(shù): 48/49頁(yè)
文件大?。?/td> 340K
代理商: HSP50210
3-48
AC Test Load Circuit
Test head capacitance.
Hold Time ISER, QSER, SSYNC FROM SERCLK
t
DSH
0
-
ns
Setup Time A0-2, C0-7 to Rising Edge of WR
t
WS
15
-
ns
Hold Time A0-2, C0-7 from Rising Edge of WR
t
WH
0
-
ns
WR to CLK
t
WC
15
-
ns, (Note 13)
SERCLK to CLK
t
SC
10
-
ns, (Note 13)
CLKtoAOUT9-0,BOUT9-0,COF,COFSYNC,SOF,SOFSYNC,
SMBLCLK, HI/LO, SLOCLK, LKINT, THRES
t
DO
-
8
ns
Read Address Low to Data Valid
t
ADO
-
26
ns
CLK to Status Out on C0-7
t
CDO
-
15
ns
WR High
t
WRH
16
-
ns
WR Low
t
WRL
16
-
ns
RD Low
t
RL
16
-
ns
RD LOW to Data Valid
t
RDO
-
15
ns
RD HIGH to Output Disable
t
ROD
-
10
ns, (Note 12)
Output Enable
t
OE
-
8
ns
Output Disable Time
t
OD
-
8
ns, (Note 12)
Output Rise, Fall Time
t
RF
-
5
ns, (Note 12)
NOTES:
11. AC tests performed with C
L
= 40 pF, I
OL
= 2mA, and I
OH
= -400mA. Input reference level for CLK is 2.0V, all other inputs 1.5V.
Test V
IH
= 3.0V, V
IHC
= 4.0V, V
IL
= 0V.
12. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
13. Set up time required to ensure action initiated by WR or SERCLK will be seen by a particular CLK.
AC Electrical Specifications
V
CC
= 5.0V
±
5%, T
A
= 0
o
C to 70
o
C (Commercial), T
A
= -40
o
C to 85
o
C (Industrial), (Note 11)
(Contin-
PARAMETER
SYMBOL
52MHz
COMMENTS
MIN
MAX
EQUIVALENT CIRCUIT
C
L
IOH
1.5V
IOL
DUT
SWITCH S1 OPEN FOR I
CCSB
AND I
CCOP
S1
±
HSP50210
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