參數(shù)資料
型號(hào): HSP50210
廠商: HARRIS SEMICONDUCTOR
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop(數(shù)字Costas鎖相環(huán))
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁數(shù): 30/49頁
文件大?。?/td> 340K
代理商: HSP50210
3-30
.
5
6
NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
LKINT Asserts Indicating End of Lock Detector Accumulation Cycle; Accumulators Ready to Read.
Set A0-2 to 5 for Reading Lock Detector.
Load Read Address Register with 3
dec
to enable the Lock Detector Phase Error Accumulator for Reading.
Set A0-2 to 3 for Phase Error (PE) Read.
Assert RD and read (Phase Error (PE) MSW; PE LSW; False Lock (FL) MSW; FL LSW).
Change Read Address to (2; 1; 0) to read various Lock Detection values.
Change Address to 4 to Initialize the Lock Detector.
Load Write Address Register with 30
dec
to initialize the Lock Detector Accumulators and Reset Integration Counters. (Only has an effect in
μ
P
mode).
Keep Address to 4 to Restart the Lock Detector.
Load Write Address Register with 25
dec
to restart the Lock Detector. (Only necessary if not in the
μ
P mode).
FIGURE 24. PROCESSOR INTERRUPT MONITOR/LOCK DETECTOR READ
1
2
3
4
5
6
7
8
9
10
WR
CLK
A0-2
C0-7
2
0
3
5
4
1
RD
P
S
1
2
PE
LSW
30
3
3
4
5
6
5
6
5
7
8
9
10
PE
MSW
FL
MSW
FL
LSW
4
25
D
S
SR-7
LKINT
CLK
A0-2
RD
4
C7-0
STATUS CAN CHANGE EVERY CLK
FIGURE 25. INTERNAL STATUS REGISTER READ
HSP50210
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