參數(shù)資料
型號(hào): HSP50210
廠商: HARRIS SEMICONDUCTOR
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop(數(shù)字Costas鎖相環(huán))
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁數(shù): 17/49頁
文件大?。?/td> 340K
代理商: HSP50210
3-17
The soft decision threshold represents a range of
magnitude values from 0.0 to
~
0.5.
Note: Since the input
to the slicer has a range of 0.0 to
~
1.0, the threshold
setting should be set to less than 1.0/3 = 0.33. This
avoids saturation.
The slicer decisions are output in either
a two’s complement or sign/magnitude format (see Soft
Decision Slicer Configuration Control Register, bit 7: Table
40). The slicer input to output mapping for a range of input
magnitudes is given in Table 7. For example, a negative
input to the slicer whose magnitude is greater than twice
the programmable threshold but less than 3x the threshold
would produce a sign/magnitude output of 110 (BINARY).
The I and Q inputs to the slicer are encoded into 3-bit soft
decisions ISOFT(2-0) and QSOFT(3-0). These signals are
routed to the OUTA(9-4) outputs by the Output
Configuration Control Register Selector bits 0-3 (see
Table 42).
Carrier Phase Error Detector
The Carrier Phase Error is computed by removing the
phase modulation from the phase output of the Cartesian
to Polar Converter. To remove the modulation, the phase
term is rotated and multiplied (modulo 2
π
) to fold the Phase
Error into an arc centered about 0
o
but encompasses the
whole plane, as shown in Figure 14. The phase rotation is
performed by adding a 4-bit two’s complement phase offset
(resolution 22.5
o
) to the 4 MSBs of the 8-bit phase term.
The multiplication is performed by left shifting the result
from 0-3 positions with the MSB’s discarded and zeros
inserted into the LSB’s. For example, Carrier Phase Error
produces I/Q constellation points which are rotated from
the expected constellation points as shown in Figure 14. By
adding an offset of 45
o
(0010 0000 binary) and multiplying
by 4 (left shift by two positions) the phase modulation is
removed, and the error is folded into a 90
o
arc centered at
0
o
. The left axis represents a decision boundary of
±
45
o
C,
implying the vertical axis is
±
22.5
o
as shown in Figure 14.
The phase offset and shift factors required for different PSK
orders is given in Table 8. Configuration of the Carrier
Phase Error Detector is done via the Carrier Phase Error
Detector Control Register, bits 0-5, (see Table 17). The
Phase Error term may be selected for output via the Output
Selector Configuration Control Register, bits 0-3 (see
Table 42).
PROBABILITY
DENSITY
FUNCTION
‘0’
‘1’
T
2
3
T
2
3
STRONGER
WEAKER
STRONGER
WEAKER
HARD DECISION
THRESHOLD
0.0
0.5
-0.5
‘1’ DECISION
‘0’ DECISION
FIGURE 13. OVERLAY OF THE HARD/SOFT DECISION
THRESHOLDS ON THE SYMBOL PROBABILITY
DENSITY FUNCTIONS (PDFs) FOR BPSK/QPSK
SIGNALS)
FS
0
1/3
1/2
-FS
THRESHOLD
MSB-1
MSB-1
1/2
1/3
THRESHOLD
MSB
MSB
MSB-1
MSB-1
TABLE 7. SLICER INPUT TO OUTPUT MAPPING
S
I
SLICER INPUT MAGNITUDE
RELATIVE TO
S
O
T
C
O
1
T
2
T
3
T
+
>
>
>
011
011
+
>
>
010
010
+
>
<
001
001
+
<
<
000
000
-
<
<
100
111
-
>
<
101
110
-
>
>
110
101
-
>
>
>
111
100
HSP50210
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