參數(shù)資料
型號: HSP50210
廠商: HARRIS SEMICONDUCTOR
元件分類: 通信及網(wǎng)絡
英文描述: Digital Costas Loop(數(shù)字Costas鎖相環(huán))
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁數(shù): 25/49頁
文件大?。?/td> 340K
代理商: HSP50210
3-25
Serial Output Controller
The frequency correction terms generated by the Symbol
and Carrier Loop Filters are output through two separate
serial interfaces. The symbol frequency offset used to close
the symbol Tracking Loop is output via the SOF and
SOFSYNC outputs. The carrier offset frequency used to
close the Carrier Tracking Loop is output via the COF and
COFSYNC outputs.
The serial output timing, identical for both of the loop filter
outputs, is shown in Figure 18. The data word is output MSB
first starting with the first rising edge of either CLK or
SLOCLK that follows the assertion of sync (COFSYNC or
SOFSYNC). The HSP50210 is configured to output the
serial data with either CLK or SLOCLK (see Serial Output
Configuration Control Registers bit 7, Table 41). The
SLOCLK output is a programmable sub-multiple of CLK
which is provided for applications requiring a slower serial
clock. In applications where the HSP50210 is used with the
HSP50110, both parts must be supplied with the same CLK
and the HSP50210 is configured to use CLK as the serial
clock. The serial output can be configured for word
containing from 8 to 40 bits.
Output Selector
The output selector determines which internal signals are
multiplexed to the AOUT9-0 and BOUT9-0 outputs. Fifteen
different output options are provided: ISOFT(2:0), QSOFT(2:0),
IEND(7:1), QEND(7:1), AGC(7:1), MAG(7:0), Phase(7:0),
FREQERR(7:1), GAINERR(7:1), BITPHERR(7:1),
CARPHERR(7:1), LKACC(6:0), LKCNT(6:0), NCOCOS(9:0),
and STATUS (6:0). These are detailed in the Output Selector
Configuration Control Register, bits 0-3 (see Table 42).
SEARCH
VERIFY
LOCK
FALSE
LOCK
PHASE ERROR ACCUMULATOR
FINISHES BEFORE
INTEGRATION COUNTER
INTEGRATION COUNTER
FINISHES BEFORE
PHASE ERROR ACCUMULATOR
PHASE ERROR
ACCUMULATOR
FINISHES BEFORE
INTEGRATION
COUNTER
INTEGRATION
COUNTER
FINISHES BEFORE
PHASE ERROR
ACCUMULATOR
AND VERIFY
COUNTER DONE
FALSE LOCK
ACCUMULATOR
BEFORE
LOCK COUNTER
FALSE
LOCK COUNTER
NOT DONE
INTEGRATION COUNTER
FINISHES BEFORE
PHASE ERROR
ACCUMULATOR AND
VERIFY COUNTER
NOT DONE
FALSE
LOCK COUNTER
DONE
INTEGRATION
COUNTER FINISHES
BEFORE
PHASE ERROR
ACCUMULATOR
PHASE ERROR
ACCUMULATOR
FINISHES BEFORE
INTEGRATION COUNTER
FIGURE 18. ACQUISITION/TRACKING STATE DIAGRAM
COF/
SOF
MSB
MSB
CLK/
COFSYNC/
SOFSYNC
SLOCLK
NOTE:
“High”.
COFSYNC and SOFSYNC shown Configured as active
FIGURE 19. SERIAL OUTPUT TIMING FOR COF AND SOF
OUTPUTS
HSP50210
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