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參數(shù)資料
| 型號： | HSP50210 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC84 |
| 文件頁數(shù)： | 23/49頁 |
| 文件大?。?/td> | 340K |
| 代理商： | HSP50210 |
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3-23
whether the Carrier Tracking Loop is locked to the input
signal.
Note: The Symbol Tracking Loop locks
independently; under most circumstances, it will lock
before the Carrier Tracking Loop locks up.
Based on the
in-lock/out-of-lock decision, either the Acquisition or Tracking
parameters are selected in the Carrier Tracking Loop, the
Symbol Tracking Loop and in the Lock Detector itself. The
Lock Detector can be configured either to make the “l(fā)ock”
decision automatically using the State Machine Control
Mode, or to collect the necessary data so that an external
microprocessor can control the acquisition/tracking process
via the Microprocessor Control Mode (see Figure 22).
In State Machine Control Mode, the Lock Detector State
Machine monitors the outputs of the Phase Error Accumulator
and the False Lock Accumulator to determine the Lock
Detector state. Accumulation effectively averages the Phase
Error and false lock count, reducing their variance. Lock is
detected by accumulating the magnitude of the Phase Error
over a predetermined interval up to 1025 symbols (the
Integration Time). When the Carrier Loop is locked, the
Integration Period will end before an overflow occurs in the
Phase Error Accumulator. At the beginning of a lock detection
cycle,thePhaseErrorAccumulatorandtheIntegrationCounter
are loaded with their respective pre-load values. With each end
bitsample,thePhaseErrorAccumulatoraddsthemagnitudeof
the current Phase Error to its accumulated sum, while the
Integration Counter decrements one count. The Lock Detector
State Machine monitors the overflow bit of the Phase Error
Accumulator and the output of the Integration Counter. If the
Phase Error Accumulator overflows before the Integration
Counter reaches zero, then the accumulated Phase Error is too
large for the Carrier Tracking Loop to be in lock and the Lock
Detector State Machine goes into the Search state (see Lock
Detector State Machine below). In the search state, the loop
parameters are reloaded with “Acquisition” rather than
“Tracking” values. When the Phase Accumulator overflows or
when the Integration Counter reaches zero, the Integration
Counterandtheaccumulatorsarere-initializedandtheprocess
begins again. The Integration Counter Pre-load corresponds to
the number of symbols over which to integrate. The Phase
Error Preload corresponds to the distance the Phase Error
Accumulator starts away from overflow. This distance divided
by the Integration Period equals the average Phase Error. The
pre-load value is calculated using:
Preload =
(EQ. 12)
where
Full scale = 2
18
-1
Full scale phase = 180
o
for CW, 90
o
for BPSK, 45
o
for QPSK,
etc;
Lock Threshold <45
o
for BPSK, <22.5
o
for QPSK, etc.
(typical after shift); and Integration Count = Integration
Period measured in symbol times.
The False Lock Detector is used to indicate false lock on
square wave data in a high SNR environment. A false lock
condition is detected by monitoring the final integration stage
in the Q branch of the Integrate and Dump Filter (see Figure
3). If the magnitude of the integration over the symbol period
is less than the integration over half a symbol period, a
possible false lock condition is detected; (integration over a
symbol period has gone from end-bit to end-bit, while
integration over half the symbol period has gone from the
previous end-bit to mid-bit). By accumulating the number of
these occurrences over the Integration Period, the Lock
Detector State Machine determines whether a false lock
condition exists. The False Lock Accumulator is used to
accumulate the number of possible false lock occurrences
over the Integration Period. The False Lock Accumulator can
also be configured to accumulate the output of the
Frequency Error Detector (see Lock Detection Configuration
Control Register bit 27: Table 34).
The Gain Error Accumulator provides a mechanism to
estimate data quality (E
s
/N
o
). The accumulator integrates
the magnitude of the gain error of the end-bit samples, over
the Integration Period.
Note: The Gain Error end-bit data
is valid only after lock has been declared, and the
demod is the tracking mode.
The accumulated value
gives an indication of the variance about the ideal
constellation points. The accumulator output is read via the
Microprocessor Interface. The Gain Error Accumulator is
always pre-loaded with zero.
For applications where stepped acquisition is used, a Dwell
Counter is provided. In this mode, the lag accumulator in the
Carrier Loop Filter is stepped to a new frequency after each
Lock Detector integration. The Dwell Counter is used to hold
off Lock Accumulator integration until the loop has a chance
to settle.
Lock Detector Control
The selection of acquisition and tracking modes is controlled
by either the internal state machine or an external
microprocessor. The internal state machine monitors the
rollover of the Phase Error Accumulator and the False Lock
Accumulator relative to the Integration Counter. Depending
on whether the accumulators or counter roll over first, the
acquisition or tracking parameters are selected for the Loop
Filters and the Lock Detector Accumulators. In addition, the
state machine controls the frequency sweep input to the
Carrier Tracking Loop.
The flow of the acquisition control is shown in the State
Diagram in Figure 17. The state machine controls the
acquisition process as described below:
Search.
The frequency uncertainty is swept by enabling the
Frequency Sweep Block to the lag path of the Carrier
Tracking Loop Filter. The acquisition parameters are enabled
to the Loop Filters and the Lock Detector Accumulators.
Phase lock is obtained when the Lock Counter rolls over
before the Phase Error Accumulator (average Phase Error is
less than the lock threshold).
Full Scale
----------------------------------------------
x 128 x Integration Count
–
HSP50210
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| HSP50214VC | Programmable Downconverter |
| HSP50214VI | Programmable Downconverter |
| HSP50214 | Programmable Downconverter |
| HSP50215VC | Digital UpConverter |
| HSP50215VI | Digital UpConverter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50210JC-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JC-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52 | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50210JI-52Z | 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter |
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