參數(shù)資料
型號(hào): HSP50210
廠商: HARRIS SEMICONDUCTOR
元件分類(lèi): 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop(數(shù)字Costas鎖相環(huán))
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁(yè)數(shù): 29/49頁(yè)
文件大?。?/td> 340K
代理商: HSP50210
3-29
TABLE 13. INTERNAL STATUS REGISTER (SR7-0) BIT MAP
NOTE: These processor signals are meant to be representative. The actual shape of the waveforms will be set by the microprocessor used. Verify
that the processor waveforms meet the parameters in the Waveforms Section of this data sheet to ensure proper operation. The Processor wave-
forms are not required to be synchronous to CLK. They are shown that way to clarify the illustration.
Load the Write Address Register with 24
dec
to halt the Lock Detector after the current integration cycle. This disables the reload of the integration
counter in the lock detector. The verify counter is not reset and will resume at the stopped value when the lock detector is restarted.
Load the Read Address Register with 3
dec
to enable the Lock Detector Phase Error Accumulator for reading.
Read Internal Status Register to monitor SR-7 to determine when the Lock Detector is stopped and ready to be read.
SR-7 goes high, indicating the Lock Detector integration cycle is complete, and ready to be read.
Read Internal Status Register and find SR-7 = 1; the Lock Detector is ready to be read.
Change Read address to (3; 2; 1; 0) for (Phase Error MSW; PE LSW; False Lock MSW; FL LSW) read.
End of Internal Status Valid Data.
Assert RD to Read Lock Detector Status
Load The Write Address Register with 30
dec
to initialize Lock Detector Accumulators and Reset the Integration counters. (Not needed for state
machine mode).
Load the Write Address Register with 25
dec
to restart the Lock Detector.
FIGURE 23. PROCESSOR MONITORING INTERNAL STATUS/READING LOCK DETECTOR
1
2
3
4
5
6
7
8
9
10
8
6
WR
CLK
A0-2
C0-7
4
2
5
4
1
3
RD
P
S
30
24
1
2
3
5
6
8
6
8
6
8
PE
MSW
0
25
D
S
SR-7
3
7
4
FL
MSW
9
FL
LSW
10
4
LOCK DETECTION STATUS READS
INTERNAL
STATUS READS
ENABLE
LD REG.
FOR READING
HALT LD
AT END OF
CYCLE
RESET
LOCK
DETECTOR
RESTART
LOCK
DETECTOR
PE
LSW
SR7=1
SR7=0
BIT
BIT DESCRIPTION
7
Lock Detector Stopped and Ready for Reading
(State Machine Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
6
Lock Detector Stopped and Ready for Reading
(Microprocessor Control Mode).
0 = Lock Detector not stopped.
1 = Lock Detector stopped, ready for read.
5
Carrier Loop Filter Lag Accumulator Load Complete. This bit
is used to determine when a 32-bit load of Carrier Lag Accu-
mulator is complete. The accumulator load is initialized by
loading the Write Address Register with 13 (decimal) as de-
scribed in Table 27.
0 = Load not complete.
1 = Load complete.
4
Symbol Tracking Loop Filter Lag Accumulator Load
Complete. This bit is used to determine when a 32-bit load
of Symbol Track Lag Accumulator is complete. The
accumulator load is initialized by loading the Write Address
Register with 19 (decimal) as described in Table 33.
0 = Load not complete.
1 = Load complete.
3
Lock. Carrier Lock state achieved by Lock Detector.
0 = Not locked.
1 = Locked.
2
Acquisition/Track. Indicates whether the Lock Detector is in
acquisition or tracking mode.
0 = Tracking Mode.
1 = Acquisition Mode.
1
Reserved.
0
Frequency Sweep Direction, defined for upper sideband sig-
nals.
0 = UP.
1 = DOWN.
BIT
BIT DESCRIPTION (Continued)
HSP50210
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