參數(shù)資料
型號: HSP50210
廠商: HARRIS SEMICONDUCTOR
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Digital Costas Loop(數(shù)字Costas鎖相環(huán))
中文描述: SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁數(shù): 31/49頁
文件大?。?/td> 340K
代理商: HSP50210
3-31
TABLE 14. DATA PATH CONFIGURATION CONTROL REGISTER
DESTINATION ADDRESS = 0
BIT
POSITION
FUNCTION
DESCRIPTION
31-27
Reserved
Reserved. Set to 0 for proper operation.
26-24
Integrate/Dump Shifter
Gain
These bits set the shifter attenuation in the Integrate/Dump Filter.
000 = No Shift (Gain = 2
0
).
001 = Right Shift 1 (Gain = 2
-1
).
010 = Right Shift 2 (Gain = 2
-2
).
011 = Right Shift 3 (Gain = 2
-3
).
100 = Right Shift 4 (Gain = 2
-4
).
Other Codes are invalid.
23-16
Input Level Detector
Threshold
This register sets the magnitude threshold for the Input Level Detector (see Input Level Detector
Section). This 8-bit value is a fractional unsigned number whose format is given by:
2
0
. 2
-1
2
-2
2
-3
2
-4
2
-5
2
-6
2
-7
.
The possible threshold values range from 0 to 1.9961 (00 - FF hex). The magnitude range for complex
inputs is 0.0 - 1.4142 while that for real inputs is 0.0 - 1.0.
Note: The algorithm used to estimate
threshold produces a maximum output of 1.375, therefore a threshold of greater than 1.375 will
never be exceeded.
15
Input Data Format Select 0 = Two’s Complement Input.
1 = Offset binary Input.
14
Serial/Parallel Input
Select
0 = Parallel Input.
1 = Serial Input.
13
Input Level Detector
Output Select
0 = HI/LO output of 1 means input
threshold.
1 = HI/LO output of 1 means input > threshold.
12
Q Input to Complex
Multiplier
0 = QIN9-0 enabled to Complex Multiplier.
1 = Q input to Complex Multiplier zeroed.
11
I Input to Complex
Multiplier
0 = IIN9-0 enabled to Complex Multiplier.
1 = I input to complex multiplier set to negative full scale (200 Hex).
10
Complex Multiplier
Bypass
0 = Data enabled to Complex Multiplier (Multiplied by output of NCO).
1 = Complex Multiplier Bypassed.
9
Demodulation/Loop
Filter Mode
Select
0 = Error detector outputs routed to Loop Filters (Normal Mode of Operation).
1 = Part functions as dual Loop Filters. The IIN9-0 input is routed to the Symbol Loop Filter; the QIN9-
0 input is routed to the Carrier Loop Filter. Data is gated into the Loop Filters with the assertion of SYNC.
8
Cartesian/Polar Input
Select
0 = Enable output of AGC Multiplier to Cartesian to Polar Converter.
1 = Enable output of Integrate and Dump Filter to the Cartesian to Polar Converter.
7
RRC Filter Enable
0 = Enable RRC filter.
1 = Bypass RRC filter.
6
Integrate and Dump
Filter Test Mode
0 = End-Symbol Samples routed to Output Formatter.
1 = Both End and Mid Symbol routed to Output Formatter: End-symbol samples occur when
SMBLCLK is high; Mid-Symbol samples occur when SMBLCLK is low.
5
Integrate and Dump
Input Select
0 = Input taken from output of Frequency Discriminator (FSK routing).
1 = Input taken from output of AGC Multiplier (Select this setting for PSK demodulation).
4-1
Integrate and Dump
Decimation Select
Bit 4 is the MSB.
1000 = No Decimation (no accumulation, no sample pair summing).
0000 = Decimation by 2 (no accumulation, sample pair summing).
0001 = Decimation by 4 (accumulate 2 samples, sample pair summing).
0010 = Decimation by 8 (accumulate 4 samples, sample pair summing).
0011 = Decimation by 16 (accumulate 8 samples, sample pair summing).
0100 = Decimation by 32 (accumulate 16 samples, sample pair summing).
All other codes are invalid.
0
OQPSK Data
De-Skew Select
0 = Disables Q channel data delay.
1 = Delays Q Channel by 1/2 Symbol time to remove OQPSK stagger.
HSP50210
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