參數(shù)資料
型號(hào)： HSP50210
廠商： HARRIS SEMICONDUCTOR
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Digital Costas Loop(數(shù)字Costas鎖相環(huán))
中文描述： SPECIALTY TELECOM CIRCUIT, PQCC84
文件頁(yè)數(shù)： 26/49頁(yè)
文件大?。?/td> 340K
代理商： HSP50210
3-26
The status bit definition is:
To simplify the output interface, a symbol clock (SMBLCLK)
is output which is synchronous to the soft bit decisions
produced by the Slicer. The SMBLCLK is a 50% duty cycle
clock whose rising edge is centered in the middle of the
output data period for both the soft bit decisions and the end-
symbol samples, as shown in Figure 19.
Microprocessor Interface
The Microprocessor Interface is used to write the
HSP50210’s Control Registers and monitor various read
points within the demodulator. Data written to the interface is
loaded into a set of four 8-bit holding registers, one Write
Address Register, or one Read Address Register. These
registers are accessed via the 3-bit address bus (A0-2) and
an 8-bit data bus (C0-7) as shown in Table 11. The R/W
column indicates whether the data is read from or written to
the given address.
Data is read from an Internal Status Register and a series of
output holding registers. The output holding registers range
in size from 8 to 32 bits, and their contents are multiplexed
out a byte at a time on C7-0 by controlling A2-0 and
asserting RD. The addresses listed in Table 11 with the R
indicator provide the address map used for reading data
from the Microprocessor Interface.
Writing to the Microprocessor Interface
The HSP50210 is configured for operation by loading a set
of thirty-two control registers which range in size from 0 to
32 bits. They are loaded by first writing the configuration
data to the Microprocessor interface’s four holding registers
and then writing the target address to the Write Address
Register as shown in Figure 19. The Control Register
Address Map and bit definitions are given in Tables 14 - 45.
The configuration data is transferred from the holding
registers to the target control register on the fourth clock
following a write to the address register. As a result, the
holding registers should not be updated any sooner than 4
CLKs after an address register write (see Figure 20).
NOTE: The holding registers which map to the unused bits of a
particular control register do not have to be loaded.
Reading from the Microprocessor Interface
The Microprocessor Interface is used to monitor
demodulator operation by providing the ability to read the
accumulator contents in the Lock Detector and Loop
Filters. In addition, the interface is used to monitor the
HSP50210’s Internal Status Register. More clearly, the
following data is available to be read:
STATUS BIT
DEFINITION
6
Carrier Tracking Loop Lock
5
Acq/Trk
4
Frequency Sweep Direction
3
High Power
2
Low Power
1
Data Rdy
TABLE 11. READ/WRITE ADDRESS MAP FOR
MICROPROCESSOR INTERFACE
R/
W
A2-0
DESCRIPTION
W
000
Input Holding Register 0. Transfers to bits 7-0 of the
target control register. Bit 0 is the LSB of the target
register.
W
001
Input Holding Register 1. Transfers to bits 15-8 of the
target control register.
W
010
Input Holding Register 2. Transfers to bits 23-16 of a
32-bit target control register.
W
011
Input Holding Register 3. Transfers to bits 31-24 of the
target control register. Bit 31 is the MSB of the 32-bit
register.
W
100
Write Address Register. The register is loaded with the
address of the control register targeted for update.
The address map for the control registers is given in
Tables 1C-32C.
NOTE: Addresses outside the range 0-31 are invalid.
SMBLCLK
ISOFT2-0/
QSOFT2-0/
IEND7-1/
QEND7-1
FIGURE 20. OUTPUT DATA CLOCK TIMING
W
101
Read Address Register. The address loaded into this
register specifies an internal read point as given the by
address map in Table 12. Addresses outside the range
0-4 are invalid.
R
000
Selects output holding register bits 7-0 for output on
C7-0 respectively. Bit 0 is the LSB of the internal hold-
ing register.
R
001
Selects output holding register bits 15-8 for output on
C7-0, respectively.
R
010
Selects output holding register bits 23-16 for output on
C7-0, respectively.
R
011
Selects output holding register bits 31-24 for output on
C7-0, respectively. Bit 31 is the MSB.
R
100
Multiplexes 8 bits of internal status out on C7-0. See
Table 13 for bit map.
TABLE 11. READ/WRITE ADDRESS MAP FOR
MICROPROCESSOR INTERFACE (Continued)
R/
W
A2-0
DESCRIPTION
HSP50210
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HSP50210JC-52 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,COMM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50210JC-52Z 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ COM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50210JI-52 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR,84 PLCC,52MHZ,IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50210JI-52Z 功能描述:上下轉(zhuǎn)換器 COSTAS DEMODULATOR 84 PLCC 52MHZ IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
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