參數(shù)資料
型號(hào)： HFA3860BIV
廠商： HARRIS SEMICONDUCTOR
元件分類(lèi)： 無(wú)繩電話/電話
英文描述： 3.3V 288-mc CPLD
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
文件頁(yè)數(shù)： 9/40頁(yè)
文件大?。?/td> 272K
代理商： HFA3860BIV
4-9
The voltages applied to pin 16, V
REFP
and pin 17, V
REFN
set the references for the internal I and Q A/D converters. In
addition, V
REFP
is also used to set the RSSI A/D converter
reference. For a nominal I/Q input of 500mV
P-P
, the
suggested V
REFP
voltage is 1.75V, and the suggested
V
REFN
is 0.86V. V
REFN
should never be less than 0.25V.
Figure 6 illustrates the suggested interface configuration for
the A/Ds and the reference circuits.
Since these A/Ds are intended to sample AC voltages, their
inputs are biased internally and they should be capacitively
coupled. The HPF corner frequency in the baseband receive
path should be less than 1kHz.
.
The A/D section includes a compensation (calibration) circuit
that automatically adjusts for temperature and component
variations of the RF and IF strips. The variations in gain of
limiters, AGC circuits, filters etc. can be compensated for up
to
±
4dB. Without the compensation circuit, the A/Ds could
see a loss of up to 1.5 bits of the 3 bits of quantization. The
A/D calibration circuit adjusts the A/D reference voltages to
maintain optimum quantization of the IF input over this
variation range. It works on the principle of setting the
reference to insure that the signal is at full scale (saturation)
a certain percentage of the time. Note that this is not an
AGC and it will compensate only for slow variations in signal
levels (several seconds).
The procedure for setting the A/D references to
accommodate various input signal voltage levels is to set the
reference voltages so that the A/D calibration circuit is
operating at half scale with the nominal input. This leaves
the maximum amount of adjustment room for circuit
tolerances.
A/D Calibration Circuit and Registers
The A/D compensation or calibration circuit is designed to
optimize A/D performance for the I and Q inputs by
maintaining the full 3-bit resolution of the outputs. There are
two registers (CR 3 AD_CAL_POS and CR 4
AD_CAL_NEG) that set the parameters for the internal I and
Q A/D calibration circuit.
Both I and Q A/D outputs are monitored by the A/D
calibration circuit as shown in Figure 7 and if either has a full
scale value, a 24-bit accumulator is incremented as defined
by parameter AD_CAL_POS. If neither has a full scale
value, the accumulator is decremented as defined by
parameter AD_CAL_NEG. The output of this accumulator is
used to drive D/A converters that adjust the A/D’s
references. Loop gain reduction is accomplished by using
only the 5 MSBs out of the 24 bits. The compensation
adjustment is updated at a 1kHz rate. The A/D calibration
circuit is only intended to remove slow component variations.
For best performance, the optimum probability that either the
I or Q A/D converter is at the saturation level was determined
to be 50%. The probability P is set by the formula:
P(AD_CAL_POS)+(1-P)(AD_CAL_NEG) = 0.
One solution to this formula for P = 1/2 is:
AD_CAL_POS = 1
AD_CAL_NEG = -1
This also sets the levels so that operation with either NOISE
or SIGNAL is approximately the same. It is assumed that the
RF and IF sections of the receiver have enough gain to
cause limiting on thermal noise. This will keep the levels at
the A/D approximately the same regardless of whether
signal is present or not. The A/D calibration is normally set to
work only while the receiver is tracking, but it can be set to
operate all the time the receiver is on or it can be turned off
and held at mid scale.
The A/D calibration circuit operation can be defined through
CR 2, bits 3 and 4. Table 3 illustrates the possible
configurations. The A/D Cal function should initially be
programmed for mid scale operation to preset it, then
programmed for either tracking mode. This initializes the part
for most rapid settling on the appropriate values.
TABLE 2. I, Q, A/D SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
Full Scale Input Voltage (V
P-P
)
0.25
0.50
1.0
Input Bandwidth (-0.5dB)
-
20MHz
-
Input Capacitance (pF)
-
5
-
Input Impedance (DC)
5k
-
-
FS (Sampling Frequency)
-
22MHz
-
0.15
μ
F
0.15
μ
F
3.9K
8.2K
9.1K
I
Q
2V
I
IN
Q
IN
V
REFP
V
REFN
HFA3860B
0.01
μ
F
0.01
μ
F
FIGURE 6. INTERFACES
TABLE 3. A/D CALIBRATION
CR 2
BIT 4
CR 2
BIT 3
A/D CALIBRATION CIRCUIT
CONFIGURATION
0
0
OFF, Reference set at mid scale.
0
1
OFF, Reference set at mid scale.
1
0
A/D_Cal while tracking only.
1
1
A/D_Cal while RX_PE active.
HFA3860B
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