4-31
CONFIGURATION REGISTER 16 ADDRESS (40h) SIGNAL FIELD DBPSK/ CCK QCOVER
Bits 7:0
This register contains an 8-bit value defining the data packet modulation as DBPSK. This value will be a 0Ah for 802.11, and
is used in the transmitted Signalling Field of the header. This value will also be used for detecting the modulation type on the
received Header.
When CR 5-bit 7 is a ‘1’, this register address points to a shadow register holding the Q cover code. The nominal value of the
Q cover code is 48h. To provide CCK functionality, this register address must be programmed in two passes. Once with CR5
bit 7 as a 1 and once with it as a 0.
CONFIGURATION REGISTER 17 ADDRESS (44h) SIGNAL FIELD DQPSK/ CCK ICOVER
Bits 7:0
This register contains the 8-bit value defining the data packet modulation as DQPSK. This value will be a 14h for operation
at a data rate of 2MBPS and is used in the transmitted Signalling Field of the header. This value will also be used for detecting
the modulation type on the received header.
When CR 5 bit 7 is a ‘1’, this register address points to a shadow register holding the I cover code. The nominal value of the
I cover code is 48h. To provide CCK functionality, this register address must be programmed in two passes. Once with CR5
bit 7 as a 1 and once with it as a 0.
CONFIGURATION REGISTER 18 ADDRESS (48h) SIGNAL FIELD BMBOK/CCK
Bits 7:0
This register contains the 8-bit value defining the data packet modulation as BMBOK. This value will be a 37h for operation
at a data rate of 5.5MBPS and is used in the transmitted Signalling Field of the header. This value will also be used for
detecting the modulation type on the received header.
CONFIGURATION REGISTER 19 ADDRESS (4Ch) SIGNAL FIELD QMBOK/CCK
Bits 7:0
This register contains the 8-bit value defining the data packet modulation as QMBOK. This value will be a 6Eh for operation
at a data rate of 11MBPS and is used in the transmitted Signalling Field of the header. This value will also be used for
detecting the modulation type on the received header.
CONFIGURATION REGISTER 20 ADDRESS (50h) TX SIGNAL FIELD
Bits 7:3
R/W, But Not Used Internally
Bit 2
0 = Normal
1 = Transmit QPSK (2MBPS) with no header, bits 1:0 must be 00 (see Tech Brief 365)
Bits 1:0
TX data Rate. Must be set at least 2
μ
s before needed in TX frame. This selects TX signal field code from the registers above.
00 = DBPSK - 11 chip sequence (1MBPS)
01 = DQPSK - 11 chip sequence (2MBPS)
10 = BMBOK - modified 8 chip Walsh sequence (5.5MBPS)
11 = QMBOK - modified 8 chip Walsh sequence (11MBPS)
CONFIGURATION REGISTER 21 ADDRESS (54h) TX SERVICE FIELD
Bits 7:0
This 8-bit register is programmed with the 8-bit value of the Service field to be transmitted in the Header. This field is reserved
for future use and should always be set to 00h.
CONFIGURATION REGISTER 22 ADDRESS (58h) TX LENGTH FIELD (HIGH)
Bits 7:0
This 8-bit register contains the higher byte (bits 8 - 15) of the transmit Length Field described in the Header. This byte
combined with the lower byte indicates the number of microseconds the data packet will take.
CONFIGURATION REGISTER 23 ADDRESS (5Ch) TX LENGTH FIELD (LOW)
Bits 7:0
This 8-bit register contains the lower byte (bits 0 - 7) of the transmit Length Field described in the Header. This byte combined
with the higher byte indicates the number of microseconds the data packet will take.
CONFIGURATION REGISTER 24 ADDRESS (60h) RX STATUS
This read only register is provided for MACs that can’t process the header fields from the RXD port.
Bits 7:6
RX signal field detected (set to 00 when RXPE inactive)
00 = DBPSK - 11 Chip Sequence (1MBPS)
01 = DQPSK - 11 Chip Sequence (2MBPS)
10 = BMBOK - modified 8 chip Walsh sequence / CCK (5.5MBPS)
11 = QMBOK - modified 8 chip Walsh sequence / CCK (11MBPS)
Bit 5
Search/Acquisition Status (set to 0 when RX_PE is inactive)
0 = Searching
1 = Carrier Acquired
HFA3860B