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參數(shù)資料
| 型號： | HFA3860BIV |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 文件頁數(shù)： | 30/40頁 |
| 文件大小： | 272K |
| 代理商： | HFA3860BIV |
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4-30
Bits 6:0
This register is used to configure the transmit scrambler with a 7-bit polynomial tap configuration. The transmit scrambler is
a 7-bit shift register, with 7 configurable taps. A logic 1 is the respective bit position enables that particular tap. The example
below illustrates the register configuration for the polynomial F(x) = 1 + X
-4
+X
-7
. Each clock is a shift left.
CONFIGURATION REGISTER 7 ADDRESS (1Ch) SCRAMBLER TAPS (Continued)
LSB
Bits (6:0)
6 5 4 3 2 1 0
X
-7
X
-6
X
-5
X
4
X
-3
X
-2
X
-1
Term
Scrambler Taps
F(x) = 1 + X
-4
+X
-7
1 0 0 1 0 0 0
CONFIGURATION REGISTER 8 ADDRESS (20h) SQ1 ACQ THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for acquisition.
This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurements made during acquisition at each antenna dwell. This threshold comparison is added with the SQ2 threshold
in registers 10 and 11 for acquisition. A lower value on this threshold will increase the probability of detection and the
probability of false alarm.
CONFIGURATION REGISTER 9 ADDRESS (24h) SQ1 ACQ THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for acquisition.
This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurement made during acquisition at each antenna dwell.
CONFIGURATION REGISTER 10 ADDRESS (28h) SQ2 ACQ THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8 - 15) of the carrier phase variance threshold used for acquisition. This
register combined with the lower byte represents a 16-bit threshold value for carrier phase variance measurement made
during acquisition at each antenna dwell and is based on the choice of the best antenna. This threshold is used with the bit
sync threshold in registers 8 and 9 to declare acquisition. A higher value in this threshold will increase the probability of
acquisition and false alarm.
CONFIGURATION REGISTER 11 ADDRESS (2Ch) SQ2 ACQ THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the carrier phase variance threshold used for acquisition.
CONFIGURATION REGISTER 12 ADDRESS (30h) SQ1 CCA THRESHOLD (HIGH)
Bits 0 - 7
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for CCA
estimation.Thisregistercombinedwiththelowerbyterepresentsa15-bitthresholdvalueforthebitsyncamplitudesignalquality
measurement made during acquisition on CCA antenna dwell. A lower value on this threshold will increase the probability of
detection and the probability of false alarm. Set the threshold according to instructions in the text.
CONFIGURATION REGISTER 13 ADDRESS (34h) SQ1 CCA THRESHOLD (LOW)
Bits 0 - 7
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for CCA. This
register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude signal quality
measurement made during acquisition on CCA antenna dwell.
CONFIGURATION REGISTER 14 ADDRESS (38h) ED OR RSSI THRESHOLD
Bit 7:6
R/W, But Not Used Internally
Bits 5:0
This register contains the value for the RSSI threshold for measuring and generating energy detect (ED). When the RSSI
exceeds the threshold ED is declared. ED indicates the presence of energy in the channel.
To disable the ED signal so that it has no affect on the CCA logic, the threshold must be set to a 3Fh (all ones).
MSB
LSB
Bits (0:5)
5 4 3 2 1 0
0 0 0 0 0 0
00h (Min)
RSSI_STAT
1 1 1 1 1 1
3Fh (Max)
CONFIGURATION REGISTER 15 ADDRESS (3Ch) SFD TIMER
Bits 7:0
This register is programmed with an 8-bit value which represents the length of time for the demodulator to search for a SFD
in a receive Header. Each bit increment represents 1 symbol period. Failure to find the SFD will result in a return to acquisition
mode.
HFA3860B
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|---|---|
| HFA3860BIV96 | nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925IA | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA96 | null2.4GHz - 2.5GHz 250mW Power Amplifier |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860BIV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860IV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860IV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
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