參數(shù)資料
型號(hào)： HFA3860BIV
廠商： HARRIS SEMICONDUCTOR
元件分類： 無(wú)繩電話/電話
英文描述： 3.3V 288-mc CPLD
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
文件頁(yè)數(shù)： 19/40頁(yè)
文件大小： 272K
代理商： HFA3860BIV
4-19
After a brief setup time as illustrated on the timeline of Figure
12, the signal begins to emerge from the demodulator.
It takes 7 more symbols to seed the descrambler before valid
data is available. This occurs in time for the SFD to be received.
At this time the demodulator is tracking and in the coherent
PSK demodulation mode it will no longer scan antennas.
One Antenna Acquisition
(Only Recommended if Multipath is Not Significant)
When only one antenna is being used, the user can delete the
antenna switch and shorten the acquisition sequence.
Figure 13 shows the single antenna acquisition timeline with an
80 symbol preamble. This scheme deletes the second antenna
dwells but performs the same otherwise. It verifies the signal
after initial detection for lower false alarm probability.
Acquisition Signal Quality Parameters
Two measures of signal quality are used to determine
acquisition. The first method of determining signal presence is
to measure the correlator output (or bit sync) amplitude. This
measure, however, flattens out in the range of high BER and
is sensitive to signal amplitude. The second measure is phase
noise and in most BER scenarios it is a better indication of
good signals plus it is insensitive to signal amplitude.
Themetricforchoosingthebest antennaisdeterminedbyCR5
bit 3. When set to a zero the antenna with the smallest phase
variance (SQ2) is chosen. This metric has shown to have a
poor measure of multipath effects and is best suited for 1 and
2MBPS operations. When set to a one, the six sidelobes (3 on
either side of the 3 centered on the bit sync peak) are summed
and compared. The antenna with the smallest sum (SQ3) is
selected. This metric is optimal for improving 5.5 and 11MBPS
operation in the presence of multipath.
CR5 bit 4 is to select the bit sync accumulation duration
used during antenna dwells. When set to a zero the
accumulation is over 15 symbols (consistent with HSP3824,
HFA3824A, HFA3860). This setting allows the user to set the
CSE and SQ1 thresholds as before and retain consistent
CSE and acquisition performance. When set to a one, the bit
sync accumulates on the last 13 symbols instead of the last
15. The SQ1 value will be numerically smaller, so CSE and
SQ1 acquisition thresholds may need adjustment. The
benefit of setting this bit is the elimination of transients (due
to antenna switching and A/D timing adjustments) in the bit
sync accumulation. This provides the best possible data for
SQ3 based antenna diversity.
The bit sync amplitude and phase noise are integrated over
each block of 16 symbols used in acquisition or over blocks of
64 symbols in the data demodulation mode. The bit sync
amplitude measurement represents the peak of the
correlation out of the PN correlator. Figure 14 shows the
correlation process. The signal is sampled at twice the chip
rate (i.e., 22MSPS). The one sample that falls closest to the
peak is used for a bit sync amplitude sample for each symbol.
This sample is called the on-time sample. High bit sync
amplitude means a good signal. The early and late samples
are the two adjacent samples and are used for tracking.
The other signal quality measurement is based on phase
noise and that is taken by sampling the correlator output at the
correlator peaks. The phase changes due to scrambling are
removed by differential demodulation during initial acquisition.
Then the phase, the phase rate and the phase variance are
measured and integrated for 16 symbols. The phase variance
is used for the phase noise signal quality measure (SQ2). Low
phase noise means a stronger received signal.
HFA3860B
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