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參數(shù)資料
| 型號(hào)： | HFA3860BIV |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | 3.3V 288-mc CPLD |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48 |
| 文件頁數(shù)： | 28/40頁 |
| 文件大?。?/td> | 272K |
| 代理商： | HFA3860BIV |
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4-28
Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CONFIGURATION REGISTER 0 ADDRESS (0h) PART/VERSION CODE
Bit 7:4
Part Code
0 = HFA3860 series
Bit 3:0
Version Code
3 = 3860B Version
CONFIGURATION REGISTER 1 ADDRESS (04h) I/O POLARITY
This register is used to define the phase of clocks and other interface signals. 00h is normal setting.
Bit 7
This controls the phase of the RX_CLK output
Logic 1 = Invert Clk
Logic 0 = Non-Inverted Clk
Bit 6
This control bit selects the active level of the MD_RDY output pin 34.
Logic 1 = MD_RDY is Active 0
Logic 0 = MD_RDY is Active 1
Bit 5
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin 32.
Logic 1 = CCA Active 1
Logic 0 = CCA Active 0
Bit 4
This control bit selects the active level of the Energy Detect (ED) output which is an output pin at the test port, pin 44.
Logic 1 = ED Active 0
Logic 0 = ED Active 1
Bit 3
This control bit selects the active level of the Carrier Sense (CRS) output pin which is an output pin at the test port, pin 45.
Logic 1 = CRS Active 0
Logic 0 = CRS Active 1
Bit 2
This control bit selects the active level of the transmit enable (TX_PE) input pin 2.
Logic 1 = TX_PE Active 0
Logic 0 = TX_PE Active 1
Bit 1
This control bit selects the phase of the transmit output clock (TXCLK) pin 4.
Logic 1 = Inverted TXCLK
Logic 0 = NON-Inverted TXCLK
Bit 0
Reserved, must be set to 0.
CONFIGURATION REGISTER 2 ADDRESS (08h) TX AND RX CONTROL
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
Bit 7
MCLK control.
0 = 44MHz
1 = 22MHz
All signal modes supported.
1 and 2MBPS, B/QPSK 11 Chip sequence mode only. Reduced power mode.
Bit 6
TX Rotation
0 = Normal
1 = Invert Q Out
Bit 5
RX Rotation
0 = Normal
1 = Invert Q IN
Bit 4
A/D Calibration
0 = A/D_CAL Off
1 = A/D_CAL On
Bit 3
A/D Calibration control (only valid if A/D Calibration is on).
0 = A/D Calibration only while in receive tracking mode (A/D Calibration set on signals only).
1 = A/D Calibration while receive RX_PE is active (in this mode, the A/D Calibration will be set primarily on noise).
Bit 2
This bit enables/disables energy detect (ED) for the CCA function.
0 = ED Off
1 = ED On
HFA3860B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HFA3860BIV96 | nullDirect Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3861BIN96 | Direct Sequence Spread Spectrum Baseband Processor |
| HFA3925IA | null2.4GHz - 2.5GHz 250mW Power Amplifier |
| HFA3925IA96 | null2.4GHz - 2.5GHz 250mW Power Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HFA3860BIV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860BIV96 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HFA3860IV | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HFA3860IV WAF | 制造商:Harris Corporation 功能描述: |
| HFA3860IV96 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:11 Mbps Direct Sequence Spread Spectrum Baseband Processor |
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