參數(shù)資料
型號(hào)： HFA3860BIV
廠商： HARRIS SEMICONDUCTOR
元件分類： 無繩電話/電話
英文描述： 3.3V 288-mc CPLD
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
文件頁數(shù)： 10/40頁
文件大小： 272K
代理商： HFA3860BIV
4-10
RSSI A/D Interface
The Receive Signal Strength Indication (RSSI) analog signal is
input to a 6-bit A/D, indicating 64 discrete levels of received
signal strength. This A/D measures a DC voltage, so its input
must be DC coupled. Pin 16 (V
REFP
) sets the reference for the
RSSI A/D converter. V
REFP
is common for the I and Q and
RSSI A/Ds. The RSSI signal is used as an input to the Clear
Channel Assessment (CCA) algorithm of the HFA3860B. The
RSSI A/D output is stored in an 6-bit register available via the
TEST Bus and the TEST Bus monitor register. CCA is further
described on page 17.
The interface specifications for the RSSI A/D are listed in
Table 4 below (V
REFP
= 1.75V).
Test Port
The HFA3860B provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. In addition pin 1 (TEST_CK) is an output that can be used
in conjunction with the data coming from the test port outputs.
The test port is programmable through configuration register
(CR28). Any signal on the test port can also be read from
configuration register (CR29) via the serial control port.
There are 32 modes assigned to the PRISM test port. Some
are only applicable to factory test.
D/A
D/A
SELECT
+FS OR -FS
COMPARE
+FS OR -FS
COMPARE
ACCUMULATOR
(25-BIT)
TEST REG
MODE 1 (7)
REG
A/DCAL
TEST REG
MODE 25 (8:0)
A/D_CAL_ACCUM
(1/4 dB PER LSB)
A/D_CAL_CK
(APPROX 1KHz)
A/D
A/D
RX_I_IN
RX_Q_IN
A/D_CK
/3
/3
A/D_CAL_POS
A/D_CAL_NEG
/8
/8
TO RSSI A/D
V
REFN
V
REFP
ANALOG
BIASES
8
5 MSBs
5
TO CORRELATOR
FIGURE 7. A/D CAL CIRCUIT
TABLE 4. RSSI A/D SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
Full Scale Input Voltage
-
-
1.15
Input Bandwidth (0.5dB)
1MHz
-
-
Input Capacitance
-
7pF
-
Input Impedance (DC)
1M
-
-
TABLE 5. TEST MODES
MODE
DESCRIPTION
TEST_CLK
TEST (7:0)
0
Quiet Test Bus
0
00
1
RX Acquisition
Monitor
Initial Detect
A/DCal, CRS, ED,
Track, SFD Detect,
Signal Field Ready,
Length Field Ready,
Header CRC Valid
2
TX Field Monitor
IQMARK
A/DCal, TXPE Inter-
nal, Preamble Start,
SFD Start, Signal
Field Start, Length
FieldStart,CRCStart,
MPDU Start
3
RSSI Monitor
RSSI Pulse
CSE Latched, CSE,
RSSI Out (5:0)
4
SQ1 Monitor
Pulse after
SQ is valid
SQ1 (7:0)
5
SQ2 Monitor
Pulse after
SQ is valid
SQ2 (7:0)
6
Correlator Lo
Rate
Sample CLK
Correlator Magnitude
(7:0)
7
Freq Test Lo
Rate
Subsample
CLK
Frequency Register
(18:11)
8
Phase Test Lo
Rate
Subsample
CLK
Phase Register (7:3)
Shift <2:0>
9
NCO Test Lo
Rate
Subsample
CLK
NCO Register (15:8)
10
(0Ah)
Bit Sync Accum
Lo Rate
Enable
Bit Sync Accum (7:3)
Shift (2:0)
HFA3860B
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