參數(shù)資料
型號(hào)： HFA3860BIV
廠商： HARRIS SEMICONDUCTOR
元件分類： 無(wú)繩電話/電話
英文描述： 3.3V 288-mc CPLD
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, PQFP48
文件頁(yè)數(shù)： 22/40頁(yè)
文件大?。?/td> 272K
代理商： HFA3860BIV
4-22
These correlators are time invariant matched filters otherwise
known as parallel correlators. They use one sample per chip for
correlation although two samples per chip are processed. The
correlator despreads the samples from the chip rate back to the
originaldatarategiving10.4dBprocessinggainfor11chipsper
bit. While despreading the desired signal, the correlator
spreads the energy of any non correlating interfering signal.
The second form of correlator is the serial correlator bank
used for detection of the MBOK or CCK modulation. For
MBOK there is a bank of eight 8 chip correlators for the I
Channel and another 8 for the Q Channel. These correlators
integrate over the symbol and are sampled at the symbol rate
of 1.375MSps. Each bank of correlators is connected to a
biggest picker that finds the correlator output with the largest
magnitude output. This finding of 1 out of 8 process
determines 3 signal bits per correlator bank. The sign of the
correlator output determines 1 more bit per bank. Thus, each
bank of correlators can determine 4 bits at 1.375 MSPS. This
is a rate of 5.5MBPS. Only the I correlator bank is used for
BMBOK. When both correlator banks are used, this becomes
twice that rate or 11Mbps.
For the CCK modes, the correlation function uses a Fast
Walsh Transform to correlate the 4 or 64 code possibilities
followed by a biggest picker. The finding of the biggest of 4 or
64 recovers 2 or 6 bits depending on the rate. The QPSK
angle of the symbol is then used to recover the last two bits.
The correlator output is then processed through the
differential decoder to demodulate the last two bits.
Data Demodulation and Tracking
Description (DBPSK and DQPSK Modes)
The signal is demodulated from the correlation peaks
tracked by the symbol timing loop (bit sync) as shown in
Figure 14. The frequency and phase of the signal is
corrected from the NCO that is driven by the phase locked
loop. Demodulation of the DPSK data in the early stages of
acquisition is done by delay and subtraction of the phase
samples. Once phase locked loop tracking of the carrier is
established, coherent demodulation is enabled for better
performance. Averaging the phase errors over 16 symbols
gives the necessary frequency information for proper NCO
operation. The signal quality known as SQ2 is the variance
in this estimate.
Configuration Register 15 sets the search timer for the SFD.
This register sets this time-out length in symbols for the
receiver. If the time out is reached, and no SFD is found, the
receiver resets to the acquisition mode. The suggested value
is # preamble symbols + 16. If several transmit preamble
lengths are used by various transmitters in a network, the
longest value should be used for the receiver settings.
Data Decoder and Descrambler Description
The data decoder that implements the desired DQPSK
coding/decoding as shown in Table 13. The data is formed
into pairs of bits called dibits. The left bit of the pair is the first
in time. This coding scheme results from differential coding
of the dibits. Vector rotation is counterclockwise for a positive
phase shift, but can be reversed with bit 5 or 6 of CR2.
For DBPSK, the decoding is simple differential decoding.
The data scrambler and descrambler are self synchronizing
circuits. They consist of a 7-bit shift register with feedback of
some of the taps of the register. The scrambler is designed
to insure smearing of the discrete spectrum lines produced
by the PN code.
One thing to keep in mind is that both the differential decoding
and the descrambling cause error extension. This causes the
errors to occur in groups of 4 and 6. This is due to two
properties of the processing. First, the differential decoding
T0 + 1 SYMBOL
CORRELATOR
OUTPUT
REPEATS
CORRELATION
PEAK
T0 + 2 SYMBOLS
T0
CORRELATOR OUTPUT IS
THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE
RECEIVED SIGNAL
SAMPLES
AT 2X CHIP
RATE
EARLY
ON-TIME
LATE
CORRELATION TIME
FIGURE 14. CORRELATION PROCESS
TABLE 13. DQPSK DATA DECODER
PHASE SHIFT
DIBIT PATTERN (D0, D1)
D0 IS FIRST IN TIME
0
00
+90
01
+180
11
-90
10
HFA3860B
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