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參數(shù)資料
| 型號(hào)： | HDMP-1022 |
| 英文描述： | Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V |
| 中文描述： | 低成本千兆速率發(fā)送/接收芯片組配備TTL的I / O |
| 文件頁(yè)數(shù)： | 37/40頁(yè) |
| 文件大小： | 321K |
| 代理商： | HDMP-1022 |
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652
Supply Bypassing and
Integrator Capacitor
Figure 20 shows the location of
the PLL integrator capacitors,
power supply capacitors and
required grounding for the Tx and
Rx chips.
Integrating Capacitor
The integrating capacitors (C2)
are required by both the Tx and
Rx to function properly. These
caps are used by the PLL for
frequency and phase lock and
directly set the stability and
lockup times. The designed value
of C2 is 0.1
μ
F, with a tolerance
of
±
10%. The internal charging
currents are scaled with the DIV0
and DIV1 settings such that the
same capacitor value works with
all four frequency bands. Larger
values of C2 improve jitter
performance, but extend the
lockup times.
Power Supply Bypassing and
Grounding
The G-LINK chip set has been
tested to work well with a single
ground plane, assuming that it is
a fairly clean ground plane. Thus,
all of the separate grounds (V
CC
,
and V
CC
_TTL) can be connected
onto this plane. The bypassing of
V
CC
to ground should be
accomplished with a capacitor
(C1) of 0.1
μ
F.
In some instances, if the VCO of
either the Tx or the Rx are at the
extreme high end, the frequency
of STRBOUT exceeds the maxi-
mum frequency allowed by the
hosts. In this case, it is recom-
mended that a diode clamp, D1,
be used across the integrating cap
C2, such that the upper frequency
HP
HDMP-1022
LOT# Tx
DATECODE
C2
D1
C1
R1
C1
R1
C1
R1
CAP0B
CAP0A
CAP1A
HP
HDMP-1024
LOT# Rx
DATECODE
C2
D1
C1
R1
C1
R1
C1
R1
R2
R2
C1 = BYPASS CAPACITOR
C2 = PLL INTEGRATOR CAPACITOR 0.1 μF
D1 = OPTIONAL CLAMPING DIODE
0.1 μF
Figure 20a. HDMP-1022 (Tx) Power Supply Bypass.
Figure 20b. HDMP-1022 (Rx) Power Supply Bypass.
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相關(guān)代理商/技術(shù)參數(shù) |
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| HDMP-1024 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
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| HDMP-1034 | 制造商:AGILENT 制造商全稱(chēng):AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱(chēng):Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
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