參數(shù)資料
型號(hào)： HDMP-1022
英文描述： Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V
中文描述： 低成本千兆速率發(fā)送/接收芯片組配備TTL的I / O
文件頁(yè)數(shù)： 17/40頁(yè)
文件大?。?/td> 321K
代理商： HDMP-1022
632
Tx I/O Definition (cont’d.)
Name
LOUT
LOUT*
Pin
14
15
Type
O-BLL
Signal
Loop Back Serial Data Output:
Output used when LOOPEN is
active. Typically this output will be used to drive the LIN, LIN* inputs
of the Rx chip.
16 or 20 Bit Word Select:
When this signal is high, the link operates
in 20 Bit data transmission mode. Otherwise, the link operates in
16 Bit mode.
Select Double Frame Mode:
When this signal is high, the PLL
expects a 1/2 speed parallel clock at STRBIN. The chip then internally
multiplies this clock and produces a full-rate parallel clock at
STRBOUT. Note that the phase relationship of STRBIN to STRBOUT
and the sampling point change with asserting MDFSEL, as shown in
the Tx timing diagram. This feature is provided so that either a 40 bit
or 32 bit word can be easily transmitted as two 20, or two 16 bit
words. When MDFSEL is low, the PLL expects a full-rate parallel
clock at STRBIN.
Ready for Data:
Output to tell the user the Link is ready to
transmit data. This pin is a retimed version of the ED input, which is
driven by the Rx chip state machine controller.
Chip Reset:
This active-low pin initializes the internal chip registers.
It should be asserted during power up for a minimum of 5 parallel-
rate clock cycles to ensure a complete reset.
Data Clock Input:
When EHCLKSEL is low, this input is phase
locked and multiplied to generate the high speed serial clock. The chip
expects a clock frequency which is equal to the input frame rate if
MDFSEL (double frame mode) is low, and 1/2 the frame rate if
MDFSEL is high. When EHCLKSEL is high, the PLL is bypassed,
and STRBIN directly becomes the high speed serial clock. Refer to
the Tx Timing diagram for the phase relationship between STRBIN,
data and STRBOUT.
Frame-rate Data Clock Output:
This output is always a frame rate
clock derived from STRBIN. With a buffer or pulled down with a 1K
resistor to GND and ac- coupled, this output is ideal for triggering an
oscilloscope for examining the serial output eye pattern DOUT or
LOUT.
Temperature Sense Diode:
Used during wafer and package test only .
It should be left open.
Logic Power Supply:
Normally 5.0 volts. This power supply is used for
the internal transmitter logic. It should be isolated from the noisy TTL
supply as well as possible.
M20SEL
73
I-TTL
MDFSEL
74
I-TTL
RFD
65
O-TTL
RST*
34
I-TTL
STRBIN
8
I-TTL
STRBOUT
76
O-TTL
TEMP
TEMP*
V
CC
31
32
7
13
23
24
43
44
52
63
64
66
72
79
T
S
相關(guān)PDF資料
PDF描述
HDMP-1024 Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片)
HDMP-1032 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器)
HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
HDMP-1512 Fibre Channel Transmitter Chipset(光纖通道傳送芯片)
HDMP-1514 Fibre Channel Receiver Chipset(光纖通道接收芯片)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1024 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034A 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set
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