參數(shù)資料
型號(hào)： HDMP-1022
英文描述： Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V
中文描述： 低成本千兆速率發(fā)送/接收芯片組配備TTL的I / O
文件頁(yè)數(shù)： 35/40頁(yè)
文件大?。?/td> 321K
代理商： HDMP-1022
650
(FLAG), and the data/control
word available pins (DAV*, CAV*),
must appear before the setup time
t
s
, and remain valid for the hold
time t
h
. Refer to
HDMP-1022 Tx
Timing
. Since the PLL of the Tx
is designed with a very high-gain
frequency/phase detector, the
relative alignment of the internal
clock and STRBIN is very tight,
and is insensitive to temperature
and other variations. The
observed external changes are
due mainly to variations in the
buffers, which are relatively small.
For convenience, the setup and
hold times are referenced back to
the user-supplied clock, STRBIN.
The actual sampling clock is
slightly advanced relative to
STRBIN due to internal delays,
and the hold time is typically
negative.
The user has to make sure that
M20SEL, FLAGSEL, DIV0, and
DIV1 have the same setting on
both Tx and Rx. The word width
of the parallel data from the host
can be either 16 bits if M20SEL =
0, or 20 bits if M20SEL = 1. Also,
the FLAG bit can be used as an
additional bit by setting
FLAGSEL=1. In the last case, the
parallel data word width is either
17 bits or 21 bits. The local
loopback test can be enabled by
setting LOOPEN high.
Single Frame Mode
(MDFSEL=0)
A block diagram showing the
single-frame mode data interface
for both the Tx and Rx, and their
associated timing diagrams are
shown in Figure 18.
In the Tx side, the expected
frequency of the input clock
STRBIN is the bit rate of the data
frame. In this case, the setup and
hold times are referenced to the
rising edge of STRBIN. The
internal clock is buffered to form
STRBOUT which appears with a
delay of T
strb
after STRBIN.
In the Rx side, the data frame,
flag bit, CAV*, DAV*, LINKRDY,
and ERROR appear with a delay
of t
d1
after the falling edge of
STRBOUT. The state machine
outputs STAT0 and STAT1 appear
with a delay of t
d2
.
Figure 18. Tx and Rx Data Interface for Single Frame Mode (MDFSEL=0).
Tx
CONFIGURATIONS
CAV*, DAV*
D00 - D19
FLAG
PLL
STRBOUT
STRBIN
Rx
CONFIGURATIONS
CAV*, DAV*, FF
LINKRDY, ERROR
D00 - D19
FLAG
STRBOUT
STAT0, STAT1
t
s
t
h
t
strb
D00 - D19
CAV*, DAV*
FLAG
STRBOUT
STRBIN
t
d2
D00 - D19
FLAG
CAV*, DAV*, FF
LINKRDY, ERROR
STAT0, STAT1
STRBOUT
t
d1
t
s
= SETUP TIME
t
h
= HOLD TIME
t
strb
= STRBIN TO STRBOUT DELAY
t
d1
= STRBOUT TO SYNCHRONOUS OUTPUTS DELAY
t
d2
= STRBOUT TO STATE MACHINE OUTPUTS DELAY
相關(guān)PDF資料
PDF描述
HDMP-1024 Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價(jià)格千兆位速率接收芯片)
HDMP-1032 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器)
HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器)
HDMP-1512 Fibre Channel Transmitter Chipset(光纖通道傳送芯片)
HDMP-1514 Fibre Channel Receiver Chipset(光纖通道接收芯片)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HDMP-1024 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034A 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set
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