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參數(shù)資料
| 型號： | HDMP-1022 |
| 英文描述： | Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V |
| 中文描述： | 低成本千兆速率發(fā)送/接收芯片組配備TTL的I / O |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 321K |
| 代理商： | HDMP-1022 |
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Rx I/O Definition (cont’d.)
Name
SMRST0*
SMRST1*
Pin
28
29
Type
I-TTL
Signal
State Machine Reset Inputs:
Each of these active-low input pins
reset the Rx state machine to the initial start-up state. This initiates
a complete PLL restart and handshake at both ends of the duplex
link. Normally, SMCRST0* is connected to a power-up reset circuit
or a host system reset signal. The SMCRST1* input is normally
connected to the Tx LOCKED output. The LOCKED signal holds the
state-machine in the start-up state until the Tx PLL is locked.
State Machine Status Outputs:
These outputs indicate the current
state-machine state. They are used to directly control the Tx ED,
Tx FF, Rx FDIS, and Rx ACTIVE lines.
Recovered Frame-rate Data Clock Output:
This output is the PLL
recovered frame rate clock. D0-D19, FLAG, DAV, CAV, FF, LINKRDY,
and ERROR should all be latched on the rising edge of STRBOUT.
External VCO Replacement Test Clock:
When TCLKSEL in
enabled, this input is used in place of the normal VCO signal,
effectively disabling the PLL and allowing the user to provide an
external retiming clock for testing.
Enable Test Clock Input:
When this input is active, the TCLK,
TCLK* inputs are used in place of the normal VCO signal. This
feature is useful both for synchronous systems and for chip testing.
Ground:
Normally 5.0 volts. This power supply is used for all the
core logic other than the output drivers.
STAT0
STAT1
27
26
O-TTL
STRBOUT
35
O-TTL
TCLK
12
I-TTL
TCLKSEL
10
I-ECL
V
CC
5
23
24
33
44
63
64
73
78
13
S
V
CC_HS
S
High Speed Supply:
Normally 5.0 volts. This ground is used to provide
clean references for the high speed DIN, DIN*, LIN, LIN* inputs.
TTL Power Supply:
Normally 5.0 volts. Used for all TTL receiver
output buffer cells.
V
CCTTL
32
52
53
72
21
22
42
62
79
80
31
41
61
74
S
GND
S
Power:
Normally 0 volts. Tie to ground.
GND
TTL
S
TTL Power:
Normally 0 volts. Tie to ground.
相關PDF資料 |
PDF描述 |
|---|---|
| HDMP-1024 | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| HDMP-1032 | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
| HDMP-1514 | Fibre Channel Receiver Chipset(光纖通道接收芯片) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1024 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034A | 制造商:HP 制造商全稱:Agilent(Hewlett-Packard) 功能描述:Transmitter/Receiver Chip Set |
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