參數(shù)資料
型號(hào): GS9090A
廠商: Gennum Corporation
英文描述: GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述: GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁數(shù): 54/69頁
文件大?。?/td> 687K
代理商: GS9090A
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
54 of 69
3.11 Parallel Data Outputs
Data outputs are valid on the rising edge of PCLK as shown in
Figure 3-13
.
Figure 3-13: PCLK to Data & Control Signal Output Timing
The data is presented in 10-bit format and may be scrambled or unscrambled,
framed or unframed.
The output data format is defined by the settings of the external SMPTE_BYPASS
and DVB_ASI pins (see
Table 3-16
). Recall that in Manual mode, these pins are
set by the application layer as inputs to the device. In Auto mode, however, the
GS9090A sets these pins as output status signals.
3.11.1 Parallel Data Bus
The parallel data outputs of the GS9090A support both LVTTL and LVCMOS
levels. These outputs use either +1.8V or +3.3V, supplied at the IO_VDD and
IO_GND pins. When interfacing with +5V logic levels, the IO_VDD pins should be
supplied with +3.3V. For a low power connection, the IO_VDD pins may be
connected to +1.8V.
All outputs, including the PCLK output, will be driven to a high-impedance state if
the RESET signal is asserted LOW with the exception of the STAT pins and the
DATA_ERROR pin which will maintain the last state they were in for the duration
that RESET is asserted.
50%
t
OH
t
OD
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
CONTROL
SIGNAL OUTPUT
DOUT[9:0]
PCLK
Table 3-16: Parallel Data Output Format
Pin Settings
Output Data Format
DOUT[9:0]
SMPTE_BYPASS
DVB_ASI
10-bit Data
DATA
LOW
LOW
10-bit Multiplexed SD
Luma / Chroma
HIGH
LOW
10-bit DVB-ASI
DVB-ASI data
LOW
HIGH
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