參數(shù)資料
型號(hào): GS9090A
廠商: Gennum Corporation
英文描述: GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述: GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁(yè)數(shù): 27/69頁(yè)
文件大?。?/td> 687K
代理商: GS9090A
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
27 of 69
NOTE 1: When the internal FIFO is configured for video mode, the H, V, and F
signals will be timed to the data output from the FIFO (see
Video Mode on
page 45
).
NOTE 2: When the GS9090A is configured for Low-latency mode, the H, V, and F
output timing will be TRS-based only as shown in
Low-latency Mode on page 57
.
Active line-based timing is not available in this mode, and the setting of the
H_CONFIG host interface bit will be ignored.
Figure 3-3: H,V,F Timing
3.7 DVB-ASI Functionality
The GS9090A enters DVB-ASI mode once the device has detected 32 consecutive
DVB-ASI words without a single word or disparity error being generated. The
device will remain in DVB-ASI mode until 32 consecutive DVB-ASI words or
disparity errors are detected, or until SMPTE TRS ID words have been detected.
The lock detect block may also drop out of DVB-ASI mode under the following
conditions:
K28.5 sync patterns in the received DVB-ASI data stream will be detected by the
device in either inverted or non-inverted form.
RESET is asserted LOW
Both AUTO/MAN and DVB_ASI are asserted LOW
LOCKED pin is LOW (i.e. the device loses lock to the input signal)
In Auto mode, the GS9090A sets the SMPTE_BYPASS pin LOW and the DVB_ASI
pin HIGH to indicate that it has locked to a DVB-ASI input data stream. When
operating in Manual mode, the application layer must set the DVB_ASI pin HIGH
to enable DVB-ASI operation. The SMPTE_BYPASS pin will be ignored.
Y/Cr/Cb DATA OUT
PCLK
H
V
F
XYZ
000
000
3FF
XYZ
000
000
3FF
H SIGNAL TIMING:
H_CONFIG = LOW (Default)
H_CONFIG = HIGH
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