參數(shù)資料
型號(hào)： GS9090A
廠商： Gennum Corporation
英文描述： GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述： GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁(yè)數(shù)： 28/69頁(yè)
文件大?。?/td> 687K
代理商： GS9090A
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
28 of 69
3.7.1 DVB-ASI 8b/10b Decoding
After serial-to-parallel conversion, the internal 10-bit data bus is fed to the DVB-ASI
8b/10b decode and word alignment block. The function of this block is to word align
the data to the K28.5 sync characters, and 8b/10b decode and bit-swap the data
to achieve bit alignment with the data outputs.
The extracted 8-bit data will be presented to DOUT [7:0], bypassing all internal
SMPTE mode data processing.
3.7.2 Status Signal Outputs
In DVB-ASI mode, the DOUT9 and DOUT8 pins will be configured as DVB-ASI
status signals WORDERR and SYNCOUT respectively.
SYNCOUT will be HIGH whenever a K28.5 sync character is present on the output.
WORDERR will be HIGH whenever the device has detected an illegal code word
or there is a running disparity error.
3.8 Data-Through functionality
The GS9090A may be configured by the application layer to operate as a simple
serial-to-parallel converter. In this mode, the device presents data to the output
data bus without performing any decoding, descrambling, or word-alignment.
Data-Through functionality is enabled only when the application layer sets the
AUTO/MAN, SMPTE_BYPASS, and DVB_ASI input pins LOW. Under these
conditions, the lock detect block allows 270Mb/s input data not conforming to
SMPTE or DVB-ASI streams to be reclocked and deserialized. If the device is in
Data-Through mode, and the internal reclocker locks to the data stream, the
LOCKED pin will be set HIGH.
If the application layer does not set the AUTO/MAN pin LOW, the GS9090A will set
the SMPTE_BYPASS and DVB_ASI signals to logic LOW if presented with a data
stream without SMPTE TRS ID words or DVB-ASI sync words. In addition, the
LOCKED pin and data bus output pins will be forced LOW.
3.9 Additional Processing Features
The GS9090A contains additional processing features that are available in SMPTE
mode only (see
SMPTE Functionality on page 24
).
3.9.1 FIFO Load Pulse
To aid in the implementation of auto-phasing and line synchronization functions,
the GS9090A will generate a FIFO load pulse to reset line-based FIFO storage.
This FIFO_LD signal is available for output on one of the multi-function output port
pins, if so programmed (see
Programmable Multi-Function Outputs on page 55
).
The FIFO_LD pulse will normally be HIGH, but will go LOW for one PCLK period,
thereby generating a FIFO write reset signal.
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