參數(shù)資料
型號(hào)： GS9090A
廠商： Gennum Corporation
英文描述： GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述： GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁(yè)數(shù)： 6/69頁(yè)
文件大?。?/td> 687K
代理商： GS9090A
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
6 of 69
1.2 Pin Descriptions
Table 1-1: Pin Descriptions
Pin
Number
Name
Timing
Type
Description
1
LF-
Analog
Input
Loop filter component connection. Connect to pin 56 (LF+) as shown in
Typical Application Circuit (Part B) on page 66
.
2
PLL_GND
Analog
Input
Power
Ground connection for phase-locked loop. Connect to GND.
3
PLL_VDD
Analog
Input
Power
Power supply connection for phase-locked loop. Connect to +1.8V DC.
4
BUFF_VDD
Analog
Input
Power
Power supply connection for digital input buffers.
When DDI/DDI are AC coupled, this pin should be left unconnected.
When DDI/DDI are DC coupled, this pin should be connected to +3.3V
as shown in
Typical Application Circuit (Part B) on page 66
.
See
Serial Digital Input on page 20
for more details.
5, 6
DDI, DDI
Analog
Input
Serial digital differential input pair.
7
BUFF_GND
Analog
Input
Power
Ground connection for serial digital input buffer. Connect to GND.
8
TERM
Analog
Input
Termination for serial digital input. AC couple to BUFF_GND
9, 11
NC
–
–
No connect.
10
VBG
Analog
Input
Bandgap filter capacitor. Connect to GND as shown in
Typical
Application Circuit (Part B) on page 66
.
12
IOPROC_EN
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal Levels are LVCMOS / LVTTL compatible.
Used to enable or disable the I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
Illegal Code Remapping
EDH CRC Error Correction
Ancillary Data Checksum Error Correction
TRS Error Correction
EDH Flag Detection
To enable a subset of these features, keep the IOPROC_EN pin HIGH
and disable the individual feature(s) in the IOPROC_DISABLE register
accessible via the host interface.
When set LOW, the device will enter low-latency mode.
NOTE: When the internal FIFO is configured for Video mode or
Ancillary Data Extraction mode, the IOPROC_EN pin must be set
HIGH (see
Internal FIFO Operation on page 45
).
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