參數(shù)資料
型號: GS9090A
廠商: Gennum Corporation
英文描述: GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述: GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁數(shù): 51/69頁
文件大?。?/td> 687K
代理商: GS9090A
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
51 of 69
Ancillary data will be written into the first half of the FIFO until it is full or until the
ANC_DATA_SWITCH bit is toggled (i.e. a HIGH-to-LOW or LOW-to-HIGH
transition). If the ANC_DATA_SWITCH bit is not toggled, extracted data will not be
written into memory after the first half of the FIFO is full (see block A in
Figure 3-12
).
When the ANC_DATA_SWITCH bit is toggled, new extracted data will be written
to the second half starting at address zero (see block B in
Figure 3-12
). The data
in the first half of the FIFO may still be read.
Once the data in the first half of the FIFO has been read, the ANC_DATA_SWITCH
may be toggled again to enable the second half of the FIFO to be read. The first
half of the FIFO will be cleared, and the device will continue to write ancillary data
to the second half of the FIFO (see block C in
Figure 3-12
).
If the ANC_DATA_SWITCH bit is toggled again, new extracted data will be written
to the first half starting at address zero (see block D in
Figure 3-12
). The data in the
second half of the FIFO may still be read.
Toggling ANC_DATA_SWITCH again will clear the second half of the FIFO and
restore the read and write pointers to the situation shown in block A. The switching
process (shown in blocks A to D in
Figure 3-12
) will continue with each toggle of
the ANC_DATA_SWITCH bit.
NOTE: At least 1100 PCLK cycles (41us) must pass between toggles of the
ANC_DATA_SWITCH bit. The ANC_DATA_SWITCH bit must be toggled at a point
in the video where no extraction is occurring (i.e. the ANC_DETECT signal is
LOW).
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