參數(shù)資料
型號： GS9090A
廠商： Gennum Corporation
英文描述： GS9090A GenLINX-R III 270Mb/s Deserializer for SDI
中文描述： GS9090A GenLINX - R的第三270Mb / s的SDI解串器
文件頁數(shù)： 29/69頁
文件大?。?/td> 687K
代理商： GS9090A
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
29 of 69
By default, the FIFO load pulse will be generated such that it is co-timed to the SAV
XYZ code word presented to the output data bus. This co-timing ensures that the
next PCLK cycle will correspond with the first active sample of the video line.
NOTE: When the internal FIFO of the GS9090A is set to operate in video mode,
the FIFO_LD pulse can be used to drive the RD_RESET input to the device (see
Video Mode on page 45
).
Figure 3-4
shows the default timing relationship between the FIFO_LD signal and
the output video data.
Figure 3-4: FIFO_LD Pulse Timing
3.9.1.1 Programmable FIFO Load Position
The position of the FIFO_LD pulse can be moved in PCLK increments from its
default position to a maximum of one full line. The offset number of PCLK's must
be programmed in the FIFO_LD_POSITION[12:0] internal register (address 28h),
via the host interface.
The FIFO_LD_POSITION[12:0] register is designed to accommodate the longest
SD line length. If the user programs a value greater than the maximum line length
at the operating SD standard, the FIFO_LD pulse will not be generated.
After a device reset, the FIFO_LD_POSITION[12:0] register is set to zero and the
FIFO_LD pulse will assume the default timing.
3.9.2 Ancillary Data Detection and Indication
The GS9090A will detect all types of ancillary data in either the vertical or horizontal
data spaces. The ANC_DETECT status signal is provided to indicate the position
of ancillary data in the output data stream. This signal is available for output on the
multi-function output port pins, if so programmed (see
Programmable
Multi-Function Outputs on page 55
).
The ANC_DETECT status signal is synchronous with PCLK and can be used as a
clock enable to external logic, or as a write enable to an external FIFO or other
memory device. The ANC_DETECT signal will be asserted HIGH whenever
ancillary data is detected in the video data stream (see
Figure 3-5
). Both 8-bit and
10-bit ancillary data preambles will be detected by the GS9090A.
NOTE 1: When the internal FIFO is configured for video mode, the ANC_DETECT
signal will be timed to the data output from the FIFO (see
Video Mode on page 45
).
NOTE 2: For performance in low latency mode, see
Low-latency Mode on page 57
.
000
3FF
000
XYZ
Y'CbCr DATA
PCLK
FIFO_LD
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