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參數(shù)資料
| 型號： | GS9090A |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9090A GenLINX-R III 270Mb/s Deserializer for SDI |
| 中文描述： | GS9090A GenLINX - R的第三270Mb / s的SDI解串器 |
| 文件頁數(shù)： | 32/69頁 |
| 文件大?。?/td> | 687K |
| 代理商： | GS9090A |
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GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
32 of 69
3.9.4 EDH Flag Detection
As described in
EDH Packet Detection on page 31
, the GS9090A can detect EDH
packets in the received data stream. The EDH flags for ancillary data, active
picture, and full field areas are extracted from the detected EDH packets and
placed in the EDH_FLAG_IN register of the device (
Table 3-5
).
When the EDH_FLAG_UPDATE bit in the DATA_FORMAT register (
Table 3-7
) is
set HIGH by the application layer, the GS9090A will update the ancillary data, full
field, and active picture EDH flags according to SMPTE RP165. The updated EDH
flags are placed in the EDH_FLAG_OUT register (
Table 3-6
). The EDH packet
output from the device will contain the updated flags.
One set of flags is provided for both fields 1 and 2. Field 1 flag data will be
overwritten by field 2 flag data.
When no EDH packets are detected (EDH_DETECT = LOW), the UES flags in the
EDH_FLAG_OUT register will be set HIGH to signify that the received signal does
not support the error detection practice. These flags are set regardless of the
setting of the EDH_FLAG_UPDATE bit.
NOTE: When EDH_FLAG_UPDATE is LOW with EDH packets in the video
stream, the content of the EDH_FLAG_OUT register is not valid and should be
ignored.
Both EDH_FLAG registers may be read by the host interface at any time during the
received frame except on the lines defined in SMPTE RP165 where these flags are
updated.
The GS9090A will also extract the CRC valid or ‘V’ bit for both active picture and
full field CRCs. The AP_CRC_V bit in the DATA_FORMAT register provides the
active picture CRC valid bit status, and the FF_CRC_V bit provides the full field
CRC valid bit status (see
Table 3-7
). When EDH_DETECT = LOW, these bits will
be cleared.
The flag register values remain set until overwritten by the decoded flags in the
next received EDH packet in the following field. When no EDH packet is detected
during vertical blanking, the flag registers will be cleared at the end of the vertical
blanking period.
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