- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄385344 > GS9090A (Gennum Corporation) GS9090A GenLINX-R III 270Mb/s Deserializer for SDI PDF資料下載
參數(shù)資料
| 型號(hào)： | GS9090A |
| 廠商： | Gennum Corporation |
| 英文描述： | GS9090A GenLINX-R III 270Mb/s Deserializer for SDI |
| 中文描述： | GS9090A GenLINX - R的第三270Mb / s的SDI解串器 |
| 文件頁(yè)數(shù)： | 48/69頁(yè) |
| 文件大?。?/td> | 687K |
| 代理商： | GS9090A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)當(dāng)前第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)
GS9090A Preliminary Data Sheet
Proprietary and Confidential
34714 - 0
February 2006
48 of 69
A write and read pointer offset may be programmed in the
FIFO_EMPTY_OFFSET[9:0] register of the host interface. If an offset value is
programmed in this register, the FIFO_EMPTY flag will be set HIGH when the read
and write pointers of the FIFO are at the same address, and will remain HIGH until
the write pointer reaches the programmed offset. Once the pointer offset has been
exceeded, the FIFO_EMPTY flag will go LOW (see block B in
Figure 3-11
).
In the case where the read pointer is originally ahead of the write pointer, the
FIFO_FULL flag will be set HIGH when both pointers arrive at the same address
(see block C in
Figure 3-11
). The application layer can use this flag to determine
when to begin reading from the device.
A read and write pointer offset may also be programmed in the
FIFO_FULL_OFFSET[9:0] register of the host interface. If an offset value is
programmed in this register, the FIFO_FULL flag will be set HIGH when the read
and write pointers of the FIFO are at the same address, and will remain set HIGH
until the read pointer reaches the programmed offset. Once the pointer offset has
been exceeded, the FIFO_FULL flag will be cleared (see block D in
Figure 3-11
).
Gating the RD_CLK Using the FIFO_EMPTY Flag
Using the asynchronous FIFO_EMPTY flag to gate RD_CLK requires external
clock gating circuity to generate a clean burst clock (see
Figure 3-9
). An example
circuit for this application is shown in
Figure 3-10
.
Figure 3-9: Burst Clock
Figure 3-10: Example Circuit to Gate RD_CLK Using the FIFO_EMPTY Flag
CORRECT
INCORRECT
FIFO_EMPTY
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
RD_CLK
GATED
RD_CLK
FIFO_EMPTY
GATED
RD_CLK
RD_CLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9090ACNE3 | GS9090A GenLINX-R III 270Mb/s Deserializer for SDI |
| GS9090 | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| GS9090-CNE3 | GS9090 GenLINX-R III 270Mb/s Deserializer for SDI and DVB-ASI |
| GS9092A | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
| GS9092ACNE3 | GS9092A GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9090A_10 | 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:GenLINX III 270Mb/s Deserializer |
| GS9090ACNE3 | 制造商:Semtech Corporation 功能描述:270Mb/s Deserializer 56-Pin QFN EP 制造商:Semtech Corporation 功能描述:270Mb/s Deserializer for SDI & ASI |
| GS9090B | 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:GenLINX III 270Mb/s Deserializer for SDI |
| GS9090B_10 | 制造商:GENNUM 制造商全稱(chēng):GENNUM 功能描述:GenLINX III 270Mb/s Deserializer for SDI |
| GS9090BCNE3 | 功能描述:RF, RFID, WIRELESS RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類(lèi)型:串行 輸出類(lèi)型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。