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參數(shù)資料
| 型號： | GS4901BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 79/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4901BCNE3 |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
79 of 95
RSVD
4Bh
–
Reserved.
–
–
Video_Control
4Ch
15-5
Reserved. Set these bits to zero when writing to 4Ch.
–
–
4Ch
4
10FID_F_pulse - set this bit HIGH to stretch the 10FID
pulse duration from 1 line to 1 field.
Reference:
Section 3.8.1 on page 57
R/W
0
4Ch
3-2
Reserved. Set these bits to zero when writing to 4Ch.
–
–
4Ch
1
Host_VID_STD - set this bit HIGH to select the output
video standard using register 4Dh instead of the
external VID_STD[5:0] pins.
The external VID_STD[5:0] pins will be ignored, but
should not be left floating.
Reference:
Section 1.4 on page 20
R/W
0
4Ch
0
Reserved. Set this bit to zero when writing to 4Ch.
–
–
VID_STD[5:0]
4Dh
15-6
Reserved. Set these bits to zero when writing to 4Dh.
–
–
4Dh
5-0
Replaces the external VID_STD[5:0] pins when
VID_From_Host (bit 1 of address 4Ch) is HIGH.
Reference:
Section 1.4 on page 20
R/W
00h
RSVD
4Eh-55h
–
Reserved
–
–
Polarity
56h
15-10
Reserved. Set these bits to zero when writing to 56h.
–
–
56h
9
AFS (GS4901B only)- set this bit HIGH to invert the
polarity of the AFS timing output signal.
By default, the AFS signal is HIGH for the duration of
the first line of the n’th video frame to indicate that the
ACLK dividers have been reset at the start of line 1 of
that frame.
NOTE: The GS4900B does not generate an AFS pulse
and will ignore the setting of this bit.
Reference:
Table 1-3
R/W
0
56h
8
10FID - set this bit HIGH to invert the polarity of the
10FID timing output signal.
By default, the 10FID signal will go HIGH for one line at
the start of the 10-field sequence.
Reference:
Table 1-3
R/W
0
56h
7
DE - set this bit HIGH to invert the polarity of the DE
timing output signal.
By default, the DE signal will be HIGH whenever pixel
information is to be displayed on the display device
Reference:
Table 1-3
R/W
0
56h
6
Reserved. Set this bit to zero when writing to 56h.
–
–
56h
5
F_Digital - set this bit HIGH to invert the polarity of the F
Digital timing output signal.
By default, the F Digital signal will be HIGH for the entire
period of field 1.
Reference:
Table 1-3
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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相關代理商/技術參數(shù) |
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| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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