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參數(shù)資料
| 型號： | GS4901BCNE3 |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 37/95頁 |
| 文件大小： | 898K |
| 代理商： | GS4901BCNE3 |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
37 of 95
3. When locking the 525-line SD output standards to the
“f/1.001”
HD input
reference standards, the device will delay all line-based output timing signals
by
Δ
VSync lines relative to the input VSYNC reference. This will occur even
when the V_Offset register is not programmed. The user may compensate for
this delay by subtracting
Δ
VSync lines from the desired vertical offset before
loading this value into the register.
The value
Δ
VSync is given by the equation:
Δ
VSync
HSYNC_IN_Period
=
where:
HSYNC_IN_Period = the period of the H reference pulse
Δ
VSYNC_HSYNC = the time difference between the leading edges of the
applied V and H reference pulses
Hsync_OUT_Period = the period of the generated H Sync output
See
Figure 3-1
. H_Feedback_Divide represents the numerator of the ratio of
the output clock frequency to the frequency of the H reference pulse.
Figure 3-1: SD-HD Calculation
4. For sync-based input references, the device will advance all line-based output
timing signals by 1 line if the value programmed in the H_Offset register is
greater than 20. The user may compensate for this advance by adding 1 line
to the desired vertical offset before loading this value into the register. In
addition, the internal V_lock and F_lock signals reported in bits 3 and 4 of
register 16h will be LOW when H_Offset = 21 only, although the device will
remained genlocked. The user may choose to mask these lock signals such
that the device will continue to report genlock under this condition.
Δ
VSYNC_HSYNC
2
(
HSYNC_OUT_Period
×
)
–
+
HSYNC
VSYNC
H Sync
V Sync
Δ
VSYNC_HSYNC
HSync_OUT_Period
HSYNC_IN_Period
Δ
VSync
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| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4911ACNE3 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS4911B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4911B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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